Example of International Journal of Reconfigurable Computing format
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Example of International Journal of Reconfigurable Computing format Example of International Journal of Reconfigurable Computing format Example of International Journal of Reconfigurable Computing format Example of International Journal of Reconfigurable Computing format Example of International Journal of Reconfigurable Computing format Example of International Journal of Reconfigurable Computing format
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Example of International Journal of Reconfigurable Computing format Example of International Journal of Reconfigurable Computing format Example of International Journal of Reconfigurable Computing format Example of International Journal of Reconfigurable Computing format Example of International Journal of Reconfigurable Computing format Example of International Journal of Reconfigurable Computing format
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open access Open Access

International Journal of Reconfigurable Computing — Template for authors

Publisher: Hindawi
Categories Rank Trend in last 3 yrs
Hardware and Architecture #111 of 157 up up by 1 rank
journal-quality-icon Journal quality:
Medium
calendar-icon Last 4 years overview: 32 Published Papers | 65 Citations
indexed-in-icon Indexed in: Scopus
last-updated-icon Last updated: 20/06/2020
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Journal Performance & Insights

CiteRatio

SCImago Journal Rank (SJR)

Source Normalized Impact per Paper (SNIP)

A measure of average citations received per peer-reviewed paper published in the journal.

Measures weighted citations received by the journal. Citation weighting depends on the categories and prestige of the citing journal.

Measures actual citations received relative to citations expected for the journal's category.

2.0

CiteRatio for International Journal of Reconfigurable Computing from 2016 - 2020
Year Value
2020 2.0
2019 2.0
2018 1.5
2017 1.2
2016 1.2
graph view Graph view
table view Table view

0.236

9% from 2019

SJR for International Journal of Reconfigurable Computing from 2016 - 2020
Year Value
2020 0.236
2019 0.217
2018 0.156
2017 0.123
2016 0.158
graph view Graph view
table view Table view

0.631

62% from 2019

SNIP for International Journal of Reconfigurable Computing from 2016 - 2020
Year Value
2020 0.631
2019 1.653
2018 0.862
2017 0.44
2016 0.708
graph view Graph view
table view Table view

insights Insights

  • This journal’s CiteRatio is in the top 10 percentile category.

insights Insights

  • SJR of this journal has increased by 9% in last years.
  • This journal’s SJR is in the top 10 percentile category.

insights Insights

  • SNIP of this journal has decreased by 62% in last years.
  • This journal’s SNIP is in the top 10 percentile category.

International Journal of Reconfigurable Computing

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Hindawi

International Journal of Reconfigurable Computing

The aim of the International Journal of Reconfigurable Computing is to serve the large community of researchers and professional engineers working on theoretical and practical aspects of reconfigurable computing. The journal seeks to promote the use of reconfigurable computing...... Read More

Hardware and Architecture

Computer Science

i
Last updated on
20 Jun 2020
i
ISSN
1687-7195
i
Impact Factor
Medium - 0.603
i
Acceptance Rate
53%
i
Frequency
Not provided
i
Open Access
Yes
i
Sherpa RoMEO Archiving Policy
Green faq
i
Plagiarism Check
Available via Turnitin
i
Endnote Style
Download Available
i
Bibliography Name
unsrt
i
Citation Type
Numbered
[25]
i
Bibliography Example
C. W. J. Beenakker. “Specular andreev reflection in graphene”. Phys. Rev. Lett., vol. 97, no. 6, 067007, 2006.

Top papers written in this journal

open accessOpen access Journal Article DOI: 10.1155/2009/501672
Analysis and enhancement of random number generator in FPGA based on oscillator rings
Knut Wold1, Chik How Tan1

Abstract:

A true random number generator (TRNG) is an important component in cryptographic systems. Designing a fast and secure TRNG in an FPGA is a challenging task. In this paper, we analyze the TRNG designed by Sunar et al. (2007) based on XOR of the outputs of several oscillator rings. We propose an enhanced TRNG with better random... A true random number generator (TRNG) is an important component in cryptographic systems. Designing a fast and secure TRNG in an FPGA is a challenging task. In this paper, we analyze the TRNG designed by Sunar et al. (2007) based on XOR of the outputs of several oscillator rings. We propose an enhanced TRNG with better randomness characteristics that does not require postprocessing and passes the statistical tests. We have shown by experiment that the frequencies of the equal length oscillator rings in the TRNG are not identical. The difference is due to the placement of the inverters in the FPGA and the resulting routing between the inverters. We have implemented our proposed TRNG in an Altera Cyclone II FPGA. Our implementation has passed the NIST and DIEHARD statistical tests with a throughput of 100 Mbps and with a usage of less than 100 logic elements in the FPGA. The restart experiments have shown that the output from our TRNG behaves truly random and not pseudorandom. read more read less

Topics:

Pseudorandom number generator (54%)54% related to the paper, Random number generation (53%)53% related to the paper
View PDF
160 Citations
open accessOpen access Journal Article DOI: 10.1155/2009/259837
FPGA interconnect topologies exploration
Zied Marrakchi1, Hayder Mrabet1, Umer Farooq1, Habib Mehrez1

Abstract:

This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in L... This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR-style Mesh. read more read less

Topics:

Tree (data structure) (53%)53% related to the paper, Network topology (52%)52% related to the paper, Scalability (52%)52% related to the paper, Place and route (51%)51% related to the paper, Benchmark (computing) (51%)51% related to the paper
View PDF
64 Citations
open accessOpen access Journal Article DOI: 10.1155/2009/908740
A reconfigurable and biologically inspired paradigm for computation using network-on-chip and spiking neural networks
Jim Harkin1, Fearghal Morgan2, Liam McDaid1, Steve Hall3, Brian McGinley2, Seamus Cawley2

Abstract:

FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures ca... FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE), incorporating low-power analogue spiking neurons, interconnected using a Network-on-Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing. read more read less

Topics:

Spiking neural network (62%)62% related to the paper, Reconfigurability (52%)52% related to the paper
View PDF
63 Citations
open accessOpen access Journal Article DOI: 10.1155/2009/219140
Pipeline FFT architectures optimized for FPGAs
Bin Zhou1, Yingning Peng2, David Hwang1

Abstract:

This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-4 FPGAs Different optimization techniques and rounding schemes were explored The implementation results achieved better performance with lower resource usage than prior art The 16-bit 1024-point FFT with the R... This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-4 FPGAs Different optimization techniques and rounding schemes were explored The implementation results achieved better performance with lower resource usage than prior art The 16-bit 1024-point FFT with the R22SDF architecture had a maximum clock frequency of 952 MHz and used 2802 slices on the Spartan-3, a throughput per area ratio of 0034 Msamples/s/slice The R4SDC architecture ran at 1238 MHz and used 4409 slices on the Spartan-3, a throughput per area ratio of 0028 Msamples/s/slice On Virtex-4, the 16-bit 1024-point R22SDF architecture ran at 2356 MHz and used 2256 slice, giving a 0104 Msamples/s/slice ratio; the 16-bit 1024-point R4SDC architecture ran at 2192 MHz and used 3064 slices, giving a 0072 Msamples/s/slice ratio The R22SDF was more efficient than the R4SDC in terms of throughput per area due to a simpler controller and an easier balanced rounding scheme This paper also shows that balanced stage rounding is an appropriate rounding scheme for pipeline FFT processors read more read less

Topics:

Pipeline (computing) (54%)54% related to the paper, Rounding (52%)52% related to the paper, Throughput (business) (52%)52% related to the paper, Clock rate (50%)50% related to the paper
View PDF
62 Citations
open accessOpen access Journal Article DOI: 10.1155/2012/752910
High performance biological pairwise sequence alignment: FPGA versus GPU versus cell BE versus GPP
Khaled Benkrid1, Ali Akoglu2, Cheng Ling1, Yang Song1, Ying Liu1, Xiang Tian1

Abstract:

This paper explores the pros and cons of reconfigurable computing in the form of FPGAs for high performance efficient computing. In particular, the paper presents the results of a comparative study between three different acceleration technologies, namely, Field Programmable Gate Arrays (FPGAs), Graphics Processor Units (GPUs... This paper explores the pros and cons of reconfigurable computing in the form of FPGAs for high performance efficient computing. In particular, the paper presents the results of a comparative study between three different acceleration technologies, namely, Field Programmable Gate Arrays (FPGAs), Graphics Processor Units (GPUs), and IBM's Cell Broadband Engine (Cell BE), in the design and implementation of the widely-used Smith-Waterman pairwise sequence alignment algorithm, with general purpose processors as a base reference implementation. Comparison criteria include speed, energy consumption, and purchase and development costs. The study shows that FPGAs largely outperform all other implementation platforms on performance per watt criterion and perform better than all other platforms on performance per dollar criterion, although by a much smaller margin. Cell BE and GPU come second and third, respectively, on both performance per watt and performance per dollar criteria. In general, in order to outperform other technologies on performance per dollar criterion (using currently available hardware and development tools), FPGAs need to achieve at least two orders of magnitude speed-up compared to general-purpose processors and one order of magnitude speed-up compared to domain-specific technologies such as GPUs. read more read less

Topics:

Performance per watt (59%)59% related to the paper, Reconfigurable computing (57%)57% related to the paper
View PDF
58 Citations
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International Journal of Reconfigurable Computing format uses unsrt citation style.

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Frequently asked questions

1. Can I write International Journal of Reconfigurable Computing in LaTeX?

Absolutely not! Our tool has been designed to help you focus on writing. You can write your entire paper as per the International Journal of Reconfigurable Computing guidelines and auto format it.

2. Do you follow the International Journal of Reconfigurable Computing guidelines?

Yes, the template is compliant with the International Journal of Reconfigurable Computing guidelines. Our experts at SciSpace ensure that. If there are any changes to the journal's guidelines, we'll change our algorithm accordingly.

3. Can I cite my article in multiple styles in International Journal of Reconfigurable Computing?

Of course! We support all the top citation styles, such as APA style, MLA style, Vancouver style, Harvard style, and Chicago style. For example, when you write your paper and hit autoformat, our system will automatically update your article as per the International Journal of Reconfigurable Computing citation style.

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5. Can I use a manuscript in International Journal of Reconfigurable Computing that I have written in MS Word?

Yes. You can choose the right template, copy-paste the contents from the word document, and click on auto-format. Once you're done, you'll have a publish-ready paper International Journal of Reconfigurable Computing that you can download at the end.

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7. Where can I find the template for the International Journal of Reconfigurable Computing?

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12. Is International Journal of Reconfigurable Computing's impact factor high enough that I should try publishing my article there?

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13. What is Sherpa RoMEO Archiving Policy for International Journal of Reconfigurable Computing?

SHERPA/RoMEO Database

We extracted this data from Sherpa Romeo to help researchers understand the access level of this journal in accordance with the Sherpa Romeo Archiving Policy for International Journal of Reconfigurable Computing. The table below indicates the level of access a journal has as per Sherpa Romeo's archiving policy.

RoMEO Colour Archiving policy
Green Can archive pre-print and post-print or publisher's version/PDF
Blue Can archive post-print (ie final draft post-refereeing) or publisher's version/PDF
Yellow Can archive pre-print (ie pre-refereeing)
White Archiving not formally supported
FYI:
  1. Pre-prints as being the version of the paper before peer review and
  2. Post-prints as being the version of the paper after peer-review, with revisions having been made.

14. What are the most common citation types In International Journal of Reconfigurable Computing?

The 5 most common citation types in order of usage for International Journal of Reconfigurable Computing are:.

S. No. Citation Style Type
1. Author Year
2. Numbered
3. Numbered (Superscripted)
4. Author Year (Cited Pages)
5. Footnote

15. How do I submit my article to the International Journal of Reconfigurable Computing?

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16. Can I download International Journal of Reconfigurable Computing in Endnote format?

Yes, SciSpace provides this functionality. After signing up, you would need to import your existing references from Word or Bib file to SciSpace. Then SciSpace would allow you to download your references in International Journal of Reconfigurable Computing Endnote style according to Elsevier guidelines.

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