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Anantha P. Chandrakasan
Researcher at Massachusetts Institute of Technology
Publications - 641
Citations - 93509
Anantha P. Chandrakasan is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: CMOS & Energy consumption. The author has an hindex of 119, co-authored 619 publications receiving 89222 citations. Previous affiliations of Anantha P. Chandrakasan include University of California, Berkeley & Brigham and Women's Hospital.
Papers
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Proceedings ArticleDOI
Energy-efficient communication protocol for wireless microsensor networks
TL;DR: The Low-Energy Adaptive Clustering Hierarchy (LEACH) as mentioned in this paper is a clustering-based protocol that utilizes randomized rotation of local cluster based station (cluster-heads) to evenly distribute the energy load among the sensors in the network.
Energy-efficient communication protocols for wireless microsensor networks
TL;DR: LEACH (Low-Energy Adaptive Clustering Hierarchy), a clustering-based protocol that utilizes randomized rotation of local cluster based station (cluster-heads) to evenly distribute the energy load among the sensors in the network, is proposed.
Journal ArticleDOI
An application-specific protocol architecture for wireless microsensor networks
TL;DR: This work develops and analyzes low-energy adaptive clustering hierarchy (LEACH), a protocol architecture for microsensor networks that combines the ideas of energy-efficient cluster-based routing and media access together with application-specific data aggregation to achieve good performance in terms of system lifetime, latency, and application-perceived quality.
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.