A
Angsuman Sarkar
Researcher at Kalyani Government Engineering College
Publications - 118
Citations - 977
Angsuman Sarkar is an academic researcher from Kalyani Government Engineering College. The author has contributed to research in topics: MOSFET & Transconductance. The author has an hindex of 14, co-authored 96 publications receiving 573 citations.
Papers
More filters
Journal ArticleDOI
Effect of gate engineering in double-gate MOSFETs for analog/RF applications
TL;DR: It is demonstrated that TM-DG MOSFET can be a viable option to enhance the performance of SOI technology for high-frequency analog applications.
Journal ArticleDOI
Analytical study of Dual Material Surrounding Gate MOSFET to suppress short-channel effects (SCEs)
Arobinda Pal,Angsuman Sarkar +1 more
TL;DR: In this article, a 2D analytical model for the Dual Material Surrounding Gate MOSFET (DMSG) by solving the Poisson equation has been proposed and verified using ATLAS TCAD device simulator.
Journal ArticleDOI
Analytical modeling and sensitivity analysis of dielectric-modulated junctionless gate stack surrounding gate MOSFET (JLGSSRG) for application as biosensor
Avik Chakraborty,Angsuman Sarkar +1 more
TL;DR: In this paper, an analytical model of dielectric-modulated junctionless gate-stack surrounding gate MOSFET for application as a biosensor is presented, where an expression for the channel-center potential is obtained by solving the 2-D Poisson's equation using a parabolic-potential approach.
Journal ArticleDOI
Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model
TL;DR: In this article, the authors report a systematic, quantitative investigation of analog and RF performance of cylindrical surrounding-gate (SRG) silicon MOSFETs and derive a pseudo-two-dimensional (2D) approach applying Gauss's law in the channel region.
Journal ArticleDOI
Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET
TL;DR: In this article, the effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire (NW) Tunnel FET (TFET) was analyzed.