J
Jason Cong
Researcher at University of California, Los Angeles
Publications - 645
Citations - 28028
Jason Cong is an academic researcher from University of California, Los Angeles. The author has contributed to research in topics: Field-programmable gate array & Computer science. The author has an hindex of 76, co-authored 594 publications receiving 24773 citations. Previous affiliations of Jason Cong include Inha University & California State University, Los Angeles.
Papers
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Proceedings ArticleDOI
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
TL;DR: This work implements a CNN accelerator on a VC707 FPGA board and compares it to previous approaches, achieving a peak performance of 61.62 GFLOPS under 100MHz working frequency, which outperform previous approaches significantly.
Journal ArticleDOI
High-Level Synthesis for FPGAs: From Prototyping to Deployment
TL;DR: AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx are used as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains.
Journal ArticleDOI
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
Jason Cong,Yuzheng Ding +1 more
TL;DR: A theoretical breakthrough is presented which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time.
Proceedings ArticleDOI
A thermal-driven floorplanning algorithm for 3D ICs
Jason Cong,Jie Wei,Yan Zhang +2 more
TL;DR: A thermal-driven 3D floorplanning algorithm with CBA representation that can reduce the wirelength by 29% and reduce the maximum on-chip temperature by 56% is proposed.
Proceedings ArticleDOI
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
TL;DR: This paper implements CNN on an FPGA using a systolic array architecture, which can achieve high clock frequency under high resource utilization, and provides an analytical model for performance and resource utilization and develops an automatic design space exploration framework.