What Video Games Have to Teach Us about Learning and Literacy

What is modal logic

House of Quality

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Models of man

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The Critique Of Pure Reason

https://cyberleninka.org/article/n/224163.pdf

A definition of systems thinking: A systems approach

The design, implementation, and experimental results for a ternary content addressable search engine chip, known as the Database Accelerator (DBA), are discussed. The DBA chip architecture is presented. It is well suited to serve as a coprocessor for a variety of logic search applications. The core of the DBA system is composed of novel high-density content addressable memory (CAM) cells capable of storing three states. The design of these cells and their support circuitry are described. The CAM cell and support circuitry were fabricated and their operation confirmed. The circuit implementation of the DMA data path is described with particular emphasis on the optimization of the multiple response resolver. The timing and control methodology, which simultaneously satisfies the complexity, speed, and robustness requirements of the DBA chip, are reported. Experimental DBA chip results that verify the full functionality and testability of the design are presented. >

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A ternary content addressable search engine

A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

Digital clock buffer circuit providing controllable delay

A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

Massively parallel computer including auxiliary vector processor

The design of a novel dynamic content addressable memory (CAM) cell suitable for high-density arrays is described. The proposed cell is capable of storing three internal states: ONE, ZERO, and `don't care' (MASK). The cell consists of five NMOS transistors of which four are used to store and access data and one is used as a diode to isolate current paths. Charge is stored on the gate of a transistor which results in nondestructive current-driven READ and MATCH operations and increases the charge storage time leading to higher reliability and improved immunization to alpha particles. Using 2-/spl mu/m design rules, buried contacts, single-level metal, and low-resistance polycide lines results in a CAM cell area of 25/spl times/22 /spl mu/m/SUP 2/, which is comparable to 64-kb static random access memory (RAM) cell areas. The CAM cell was successfully fabricated using a 4-/spl mu/m NMOS process and its operation was verified with a 2/spl times/3-bit array.

Jon Wade

Papers

A definition of systems thinking: A systems approach

A ternary content addressable search engine

Digital clock buffer circuit providing controllable delay

Massively parallel computer including auxiliary vector processor

Dynamic cross-coupled bit-line content addressable memory cell for high-density arrays