Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

Metal interconnections are expected to become the limiting factor for the performance of electronic systems as transistors continue to shrink in size. Replacing them by optical interconnections, at different levels ranging from rack-to-rack down to chip-to-chip and intra-chip interconnections, could provide the low power dissipation, low latencies and high bandwidths that are needed. The implementation of optical interconnections relies on the development of micro-optical devices that are integrated with the microelectronics on chips. Recent demonstrations of silicon low-loss waveguides, light emitters, amplifiers and lasers approach this goal, but a small silicon electro-optic modulator with a size small enough for chip-scale integration has not yet been demonstrated. Here we experimentally demonstrate a high-speed electro-optical modulator in compact silicon structures. The modulator is based on a resonant light-confining structure that enhances the sensitivity of light to small changes in refractive index of the silicon and also enables high-speed operation. The modulator is 12 micrometres in diameter, three orders of magnitude smaller than previously demonstrated. Electro-optic modulators are one of the most critical components in optoelectronic integration, and decreasing their size may enable novel chip architectures.

Micrometre-scale silicon electro-optic modulator

We present a novel waveguide geometry for enhancing and confining light in a nanometer-wide low-index material. Light enhancement and confinement is caused by large discontinuity of the electric field at highindex-contrast interfaces. We show that by use of such a structure the field can be confined in a 50-nm-wide low-index region with a normalized intensity of 20 mm 22 . This intensity is approximately 20 times higher than what can be achieved in SiO2 with conventional rectangular waveguides. © 2004 Optical Society of America OCIS codes: 030.4070, 130.0130, 130.2790, 230.7370, 230.7380, 230.7390, 230.7400. Recent results in integrated optics have shown the ability to guide, bend, split, and f ilter light on chips by use of optical devices based on high-index-contrast waveguides. 1–5 In all these devices the guiding mechanism is based on total internal ref lection (TIR) in a highindex material (core) surrounded by a low-indexmaterial (cladding); the TIR mechanism can strongly confine light in the high-index material. In recent years a number of structures have been proposed to guide or enhance light in low-index materials, 6–1 1 relying on external ref lections provided by interference effects. Unlike TIR, the external ref lection cannot be perfectly unity; therefore the modes in these structures are inherently leaky modes. In addition, since interference is involved, these structures are strongly wavelength dependent. Here we show that the optical field can be enhanced and conf ined in the low-index material even when light is guided by TIR. For a high-index-contrast interface, Maxwell’s equations state that, to satisfy the continuity of the normal component of electric f lux density D, the corresponding electric field (E-field) must undergo a large discontinuity with much higher amplitude in the low-index side. We show that this discontinuity can be used to strongly enhance and confine light in a nanometer-wide region of low-index material. The proposed structure presents an eigenmode, and it is compatible with highly integrated photonics technology. The principle of operation of the novel structure can be illustrated by analysis of the slab-based structure shown in Fig. 1(a), where a low-index slot is embedded between two high-index slabs (shaded regions). The novel structure is hereafter referred to as a slot waveguide. The slot waveguide eigenmode can be seen as being formed by the interaction between the fundamental eigenmodes of the individual slab waveguides. Rigorously, the analytical solution for the transverse E-field profile Ex of the fundamental TM eigenmode of the slab-based slot waveguide is

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Guiding and confining light in void nanostructure.

Topological edge states of light are observed in a two-dimensional array of coupled optical ring resonators, which induce a virtual magnetic field for photons using silicon-on-insulator technology. The edge states are experimentally demonstrated to be robust against intrinsic and introduced disorder, which is a hallmark of topological order.

Imaging topological edge states in silicon photonics

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.

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Rationale and challenges for optical interconnects to electronic chips

Compact optical channel dropping filters incorporating side-coupled ring resonators as small as 3 /spl mu/m in radius are realized in silicon technology. Quality factors up to 250, and a free-spectral range (FSR) as large as 24 nm are measured. Such structures can be used as fundamental building blocks in more sophisticated optical signal processing devices.

Ultra-compact Si-SiO 2 microring resonator optical channel dropping filters

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

As the complexity of IT systems increases, performance management and capacity planning become the largest and most difficult expenses to control. New methodologies and modeling techniques that explain large-system behavior and help predict their future performance are now needed to effectively tackle the emerging performance issues. With the multi-tier architecture paradigm becoming an industry standard for developing scalable client-server applications, it is important to design effective and accurate performance prediction models of multi-tier applications under an enterprise production environment and a real workload mix. To accurately answer performance questions for an existing production system with a real workload mix, we design and implement a new capacity planning and anomaly detection tool, called R-Capriccio, that is based on the following three components: i) a Workload Profiler that exploits locality in existing enterprise web workloads and extracts a small set of most popular, core client transactions responsible for the majority of client requests in the system; ii) a Regression-based Solver that is used for deriving the CPU demand of each core transaction on a given hardware; and iii) an Analytical Model that is based on a network of queues that models a multi-tier system. To validate R-Capriccio, we conduct a detailed case study using the access logs from two heterogeneous production servers that represent customized client accesses to a popular and actively used HP Open View Service Desk application.

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R-Capriccio: a capacity planning and anomaly detection tool for enterprise services with live workloads

The silicon/silicon dioxide (Si/SiO2) materials system provides a high index contrast waveguide platform compatible with existing monolithic microelectronic fabrication processes. The large index difference between the Si and SiO2 ((Delta) n approximately equals 2.0) allows the miniaturization of waveguide cross-sectional dimensions: single-mode strip waveguides with 0.2 X 0.5 micrometers cross-sections are possible. Additionally, right angle waveguide bends with radii of 2.0 micrometers can be fabricated with insertion loss of less than 1.0 dB. Bend radii of 250 micrometers or more are required to achieve the same performance in less confined waveguide systems such as GaAs/AlGaAs. The high confinement of the Si/SiO2 system also allows Y-branch power splitters with splitting angles greater than 20 degree(s) to operate with low loss. The combination of small cross- section, small bend radius, and large splitting angle provides a highly compact light guiding technology. Calculations of the loss due to 90 degree(s) bends in these waveguides and preliminary loss measurements for bends from 2.0 to 100.0 micrometers in radius are reported. Y-branch power splitters are analyzed and measurements of branches from 2 degree(s) to 40 degree(s) are presented.

Small radius bends and large angle splitters in SOI waveguides

A method comprises receiving, by a workload profiler, a representative workload of a computing system under analysis. The workload profiler determines a workload profile of the computing system that reflects a transaction mix that varies over times. A capacity analyzer receives the workload profile, and determines a maximum capacity of the computing system under analysis for serving the workload profile while satisfying a defined quality of service (QoS) target.

Wayne Greene

Papers

Ultra-compact Si-SiO 2 microring resonator optical channel dropping filters

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

R-Capriccio: a capacity planning and anomaly detection tool for enterprise services with live workloads

Small radius bends and large angle splitters in SOI waveguides

System and method for capacity planning for computing systems