Artificial Neural Networks have dramatically improved performance for many machine learning tasks. We demonstrate a new architecture for a fully optical neural network that enables a computational speed enhancement of at least two orders of magnitude and three orders of magnitude in power efficiency over state-of-the-art electronics.

Deep learning with coherent nanophotonic circuits

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Photonic systems for high-performance information processing have attracted renewed interest. Neuromorphic silicon photonics has the potential to integrate processing functions that vastly exceed the capabilities of electronics. We report first observations of a recurrent silicon photonic neural network, in which connections are configured by microring weight banks. A mathematical isomorphism between the silicon photonic circuit and a continuous neural network model is demonstrated through dynamical bifurcation analysis. Exploiting this isomorphism, a simulated 24-node silicon photonic neural network is programmed using “neural compiler” to solve a differential system emulation task. A 294-fold acceleration against a conventional benchmark is predicted. We also propose and derive power consumption analysis for modulator-class neurons that, as opposed to laser-class neurons, are compatible with silicon photonic platforms. At increased scale, Neuromorphic silicon photonics could access new regimes of ultrafast information processing for radio, control, and scientific computing.

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Neuromorphic photonic networks using silicon photonic weight banks.

With the proliferation of ultrahigh-speed mobile networks and internet-connected devices, along with the rise of artificial intelligence (AI)1, the world is generating exponentially increasing amounts of data that need to be processed in a fast and efficient way. Highly parallelized, fast and scalable hardware is therefore becoming progressively more important2. Here we demonstrate a computationally specific integrated photonic hardware accelerator (tensor core) that is capable of operating at speeds of trillions of multiply-accumulate operations per second (1012 MAC operations per second or tera-MACs per second). The tensor core can be considered as the optical analogue of an application-specific integrated circuit (ASIC). It achieves parallelized photonic in-memory computing using phase-change-material memory arrays and photonic chip-based optical frequency combs (soliton microcombs3). The computation is reduced to measuring the optical transmission of reconfigurable and non-resonant passive components and can operate at a bandwidth exceeding 14 gigahertz, limited only by the speed of the modulators and photodetectors. Given recent advances in hybrid integration of soliton microcombs at microwave line rates3-5, ultralow-loss silicon nitride waveguides6,7, and high-speed on-chip detectors and modulators, our approach provides a path towards full complementary metal-oxide-semiconductor (CMOS) wafer-scale integration of the photonic tensor core. Although we focus on convolutional processing, more generally our results indicate the potential of integrated photonics for parallel, fast, and efficient computational hardware in data-heavy AI applications such as autonomous driving, live video processing, and next-generation cloud computing services.

Parallel convolutional processing using an integrated photonic tensor core.

We present an adjoint-based optimization for electromagnetic design. It embeds commercial Maxwell solvers within a steepest-descent inverse-design optimization algorithm. The adjoint approach calculates shape derivatives at all points in space, but requires only two “forward” simulations. Geometrical shape parameterization is by the level set method. Our adjoint design optimization is applied to a Silicon photonics Y-junction splitter that had previously been investigated by stochastic methods. Owing to the speed of calculating shape derivatives within the adjoint method, convergence is much faster, within a larger design space. This is an extremely efficient method for the design of complex electromagnetic components.

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Adjoint shape optimization applied to electromagnetic design.

A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.

Compact and low loss Y-junction for submicron silicon waveguide

We demonstrate compact, broadband, ultralow loss silicon waveguide crossings operating at 1550 nm and 1310 nm. Cross-wafer measurement of 30 dies shows transmission insertion loss of − 0.028 ± 0.009 dB for the 1550 nm device and − 0.017 ± 0.005 dB for the 1310 nm device. Both crossings show crosstalk lower than − 37 dB. The devices were fabricated in a CMOS-compatible process using 248 nm optical lithography with a single etch step.

Ultralow loss single layer submicron silicon waveguide crossing for SOI optical interconnect

There has been great interest in the silicon platform as a material system for integrated photonics. A key challenge is the development of a low-power, low drive voltage, broadband modulator. Drive voltages at or below 1 Vpp are desirable for compatibility with CMOS processes. Here we demonstrate a CMOS-compatible broadband traveling-wave modulator based on a reverse-biased pn junction. We demonstrate operation with a drive voltage of 0.63 Vpp at 20 Gb/s, a significant improvement in the state of the art, with an RF energy consumption of only 200 fJ/bit.

Ultralow drive voltage silicon traveling-wave modulator

Something very surprising has been happening in photonics recently: the same foundries and processes that were developed to build transistors are being repurposed to build chips that can generate, detect, modulate, and otherwise manipulate light. This is pretty counterintuitive, since the electronics industry spends billions of dollars to develop tools, processes, and facilities that lend themselves to building the very best transistors without any thought about how to make these processes compatible with photonics (with the obvious exception of the processes designed to make CMOS and CCD camera chips).

Silicon Photonics: The Next Fabless Semiconductor Industry

We report a Ge-on-Si photodetector without doped Ge or Ge-metal contacts. Despite the simplified fabrication process, the device shows a responsivity of 1.14 A/W at -4 V reverse bias and 1.44 A/W at -12V, at 1550 nm wavelength. Dark current is less than 1µA under both bias conditions. We also demonstrate open eye diagrams at 40Gb/s.

Yi Zhang

Papers

Compact and low loss Y-junction for submicron silicon waveguide

Ultralow loss single layer submicron silicon waveguide crossing for SOI optical interconnect

Ultralow drive voltage silicon traveling-wave modulator

Silicon Photonics: The Next Fabless Semiconductor Industry

A high-responsivity photodetector absent metal-germanium direct contact