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Journal ArticleDOI

Five-Input Majority Gate, a New Device for Quantum-Dot Cellular Automata

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TLDR
Simulation results demonstrate that the proposed design of majority gates and Full-Adder resulted in significant improvements in designing logical circuits.
Abstract
Science and Research Branch of IAU, Tehran, IranQuantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing atnano-scale. The principle logic element in QCA is majority gate. In this paper, a novel design for5-input majority gate is presented. A 5-input majority gate study has been proposed; however thisstudy has changed the scheme of basic QCA cells. The new proposed device reduces cell countsand area and uses conventional form of QCA cells. Accuracy of this design is proven by applyingsome simple physical substantiation and QCADesigner tool is used for verifying majority circuitlayout and functionality. Furthermore, a QCA Full-Adder is constructed using the new proposeddesign. Simulation results demonstrate that the proposed design of majority gates and Full-Adderresulted in significant improvements in designing logical circuits.

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Citations
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Journal ArticleDOI

A new quantum-dot cellular automata full-adder

TL;DR: In current study, the new layout of all single bit full adders in the quantum cellular automata's technology is introduced and in comparison with existing schemes, the suggested circuit has fewer cells and smaller area.
Journal ArticleDOI

Design of energy-efficient and robust ternary circuits for nanotechnology

TL;DR: These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes, which makes them very suitable for the multiple- V t design method.
Journal ArticleDOI

Designing efficient QCA logical circuits with power dissipation analysis

TL;DR: A comprehensive power dissipation analysis as well as a structural analysis over the previously published five-input majority gates is performed and reveals that the proposed designs have significant improvements in contrast to counterparts from implementation requirements and power consumption aspects.
Journal ArticleDOI

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata

TL;DR: A new robust five-input majority gate is first presented, which is appropriate for implementation of simple and efficient QCA circuits in single layer and has a simple and robust structure that helps achieving minimal area, as well as reduction in hardware requirements and clocking zone numbers.
Journal ArticleDOI

New robust QCA D flip flop and memory structures

TL;DR: Using a robust 2:1 multiplexer, efficient level triggered and edge triggered QCA D flip flops and a memory cell with set/reset ability will be introduced and results demonstrate that the proposed desgins have efficient structures in terms of area, delay and complexity.
References
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Proceedings ArticleDOI

Quantum-dot cellular automata adders

TL;DR: A novel quantum-dot cellular automata adder design is presented that reduces the number of QCA cells compared to previously reported designs and requires only about 70% of the hardware compared to previous designs with the same speed and clocking performance.
Proceedings ArticleDOI

Logic optimization for majority gate-based nanoelectronic circuits

TL;DR: An efficient majority logic optimizer is proposed to synthesize majority gate-based nanoelectronic circuits and a novel sharing and mapping scheme is proposed in order to achieve simple synthesized circuits and high synthesis speed.
Proceedings ArticleDOI

Design and characterization of an and-or-inverter (AOI) gate for QCA implementation

TL;DR: A detailed simulation-based analysis of the AOI gate is presented as well as the characterization of QCA defects and study of their effects at logic level, for a novel complex and universal QCA gate: the And-Or-Inverter (AOI) gate.
Proceedings ArticleDOI

Serial Parallel Multiplier Design in Quantum-dot Cellular Automata

TL;DR: Two types of serial parallel multipliers are designed and simulated with several different operand sizes and those designs are compared in terms of complexity, area, and latency.
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