Scheduling semiconductor wafer fabrication

TLDR: In this paper, a variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer fabrication, and the simulation results indicate that scheduling has a significant impact on average throughput time, with larger improvements coming from discretionary imput control than from lot sequencing.

Abstract: The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer fabrication. Certain of these scheduling rules are derived by restricting attention to the sub-set of stations that are heavily utilized, and by using a Brownian network model, which approximates a multi-class queuing network model with dynamic control capability. Three versions of the wafer fabrication model, which differ only by the number of servers present at particular stations, are studied. The three versions have one, two, and four stations, respectively, that are heavily utilized (near 90% utilization). The simulation results indicate that scheduling has a significant impact on average throughput time, with larger improvements coming from discretionary imput control than from lot sequencing. The effects that specific sequencing rules have are highly dependent on both the type of input control used and the number of bottleneck stations in the fabrication. >