Two-dimensional crystals are emerging materials for nanoelectronics. Development of the field requires candidate systems with both a high carrier mobility and, in contrast to graphene, a sufficiently large electronic bandgap. Here we present a detailed theoretical investigation of the atomic and electronic structure of few-layer black phosphorus (BP) to predict its electrical and optical properties. This system has a direct bandgap, tunable from 1.51 eV for a monolayer to 0.59 eV for a five-layer sample. We predict that the mobilities are hole-dominated, rather high and highly anisotropic. The monolayer is exceptional in having an extremely high hole mobility (of order 10,000 cm(2) V(-1) s(-1)) and anomalous elastic properties which reverse the anisotropy. Light absorption spectra indicate linear dichroism between perpendicular in-plane directions, which allows optical determination of the crystalline orientation and optical activation of the anisotropic transport properties. These results make few-layer BP a promising candidate for future electronics.

/pdf/high-mobility-transport-anisotropy-and-linear-dichroism-in-hvrytks3d2.pdf

High-mobility transport anisotropy and linear dichroism in few-layer black phosphorus

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

https://iopscience.iop.org/article/10.1088/0034-4885/69/2/R02/pdf

High dielectric constant gate oxides for metal oxide Si transistors

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin (1.4 nm) that its leakage current is too large. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or 'high K' gate oxides such as hafnium oxide and hafnium silicate. Little was known about such oxides, and it was soon found that in many respects they have inferior electronic properties to SiO2 ,s uch as a tendency to crystallise and a high concentration of electronic defects. Intensive research is underway to develop these oxides into new high quality electronic materials. This review covers the choice of oxides, their structural and metallurgical behaviour, atomic diffusion, their deposition, interface structure and reactions, their electronic structure, bonding, band offsets, mobility degradation, flat band voltage shifts and electronic defects. The use of high K oxides in capacitors of dynamic random access memories is also covered.

/pdf/high-dielectric-constant-oxides-cotu2e70vd.pdf

High dielectric constant oxides

Newly fabricated few-layer black phosphorus and its monolayer structure, phosphorene, are expected to be promising for electronic and optical applications because of their finite direct band gaps and sizable but anisotropic electronic mobility. By first-principles simulations, we show that this unique anisotropic free-carrier mobility can be controlled by using simple strain conditions. With the appropriate biaxial or uniaxial strain (4–6%), we can rotate the preferred conducting direction by 90°. This will be useful for exploring unusual quantum Hall effects and exotic electronic and mechanical applications based on phosphorene.

Strain-Engineering the Anisotropic Electrical Conductance of Few-Layer Black Phosphorus

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

https://www-inst.eecs.berkeley.edu/~ee230/sp08/takagi%20universal%20mobility%20I%201994.pdf

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

For part I see ibid., vol.41, no.12, pp.2357-62 (1994). This paper reports the studies of the inversion layer mobilities in n-channel MOSFET's fabricated on Si wafers with three surface orientations ([100], [110], and [111]) from the viewpoint of the universal relationship against the effective field, E/sub eff/(=q(N/sub dpl/+/spl eta//spl middot/N/sub s/)//spl epsi/Si). It is found that the universality does hold for the electron mobilities on [110] and [111], when the value of /spl eta/ is taken to be 1/3, different from the electron mobility on [100], where /spl eta/ is 1/2. Also, the E/sub eff/ dependence of the electron mobility is found to differ among [100], [110], and [111] surfaces. This is attributed to the differences in the E/sub eff/ dependence of the mobility limited by surface roughness scattering among the orientations. The origins of E/sub eff/ and /spl eta/ are discussed on the basis of the relaxation time approximation for a 2DEG (2-dimensional electron gas). While the surface orientation dependence of /spl eta/ in phonon scattering can be understood in terms of the subband occupation, it is found that the theoretical formulation of surface roughness scattering, used currently, needs to be refined in order to explain the differences in E/sub eff/ dependence and the value of /spl eta/ among the three orientations. >

https://www-inst.eecs.berkeley.edu/~ee230/sp08/takagi%20universal%20mobility%20II%201994.pdf

On the universality of inversion layer mobility in Si MOSFET's: Part II-effects of surface orientation

Thinning effects on the device characteristics of silicon-on-insulator (SOI) MOSFETs are discussed. Two-dimensional/two-carrier device simulation revealed the following advantages. An n-channel MOSFET with 500-AA-SOI thickness exhibited a high-punchthrough resistance as well as an improved subthreshold swing down to a deep submicrometer region, even if the film was nearly intrinsic. A capacitance coupling model has been proposed to explain these subthreshold characteristics. The kink elimination effect, which was attributed to a significantly reduced hole density in the SOI film, was reproduced. The low-field channel mobility exhibited a significant increase, which was ascribed to a decrease in the vertical electric field. Moreover, the current-overshoot phenomenon associated with the switching operation was suppressed. Excess holes recombine with electrons quickly after the gate turn-on, bringing about a stabilized potential in the SOI substrate. Experiments were also carried out to verify the simulation. >

Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film

The dependence of MOSFET gate controllability on the field-isolation scheme is investigated using three-dimensional simulation. It is found that a fully-recessed-oxide (trench) isolated MOSFET has a steep subthreshold characteristic and high transconductance in comparison with a nonrecessed device. These features result from the small depletion capacitance due to the crowding of the gate's fringing field at the channel edge. It is also found that the gate and diffused line capacitances in the case of fully-recessed-oxide isolation are small, so that high switching speed operation can be expected. These features are enhanced with a reduction in the channel width, especially for lower-submicrometer-width MOSFETs. A drawback of a fully-recessed-oxide MOSFETs is its low threshold voltage. However, the leakage current is not as large as that inferred from the inverse narrow-channel effect because of its steep subthreshold characteristic. Several countermeasures for this low threshold voltage are discussed. >

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

This paper describes the dependence of MOSFET gate-controllability on the field isolation scheme. It is found that a fully-recessed oxide (trench) isolated MOSFET has a sharp cutoff characteristic and high transconductance in comparison with a non-recessed one. These features of the fully-recessed oxide MOSFET are due to the crowding of the gate's fringing field at the channel edge. It is also found that the gate and diffused line capacitances for the fully-recessed oxide isolation are small so that high switching speed operation can be expected.

http://ieeexplore.ieee.org/iel5/9953/31997/01487466.pdf

H. Tango

Papers

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

On the universality of inversion layer mobility in Si MOSFET's: Part II-effects of surface orientation

Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

Steep subthreshold characteristic and enhanced transconductance of fully-recessed oxide (trench) isolated 1/4 µm width MOSFETs

H. Tango

Papers

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

On the universality of inversion layer mobility in Si MOSFET's: Part II-effects of surface orientation

Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

Steep subthreshold characteristic and enhanced transconductance of fully-recessed oxide (trench) isolated 1/4 &#181;m width MOSFETs

Steep subthreshold characteristic and enhanced transconductance of fully-recessed oxide (trench) isolated 1/4 µm width MOSFETs