Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin-Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

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Neuromorphic Silicon Neuron Circuits

The matching properties of the threshold voltage, substrate factor and current factor of MOS transistors have been analysed and measured. Improvements of the existing theory are given, as well as extensions for long distance matching and rotation of devices. The matching results have been verified by measurements and calculations on a band-gap reference circuit.

Matching properties of MOS transistors

A novel approach for the readout of a TPC at the future linear collider is to use a CMOS pixel detector combined with some kind of gas gain grid. A first test using the photon counting chip Medipix2 with GEM or Micromegas demonstrated the feasibility of such an approach. Although this experiment demonstrated that single primary electrons could be detected the chip did not provide information on the arrival time of the electron in the sensitive gas volume nor did it give any indication of the quantity of charge detected. The Timepix chip uses an external clock with a frequency of up to 100 MHz as a time reference. Each pixel contains a preamplifier, a discriminator with hysteresis and 4-bit DAC for threshold adjustment, synchronization logic and a 14-bit counter with overflow control. Moreover, each pixel can be independently configured in one of four different modes: masked mode: pixel is off, counting mode: 1-count for each signal over threshold, TOT mode: the counter is incremented continuously as long as the signal is above threshold, and arrival time mode: the counter is incremented continuously from the time the first hit arrives until the end of the shutter. The chip resembles very much the Medipix2 chip physically and can be readout using slightly modified versions of the various existing systems. This paper presents the main features of the new design, electrical measurements and some first images.

Timepix, a 65k programmable pixel readout chip for arrival time, energy and/or photon counting measurements

This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-/spl mu/m digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding /spl plusmn/1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.

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A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line

Neural-network training can be slow and energy intensive, owing to the need to transfer the weight data for the network between conventional digital memory chips and processor chips. Analogue non-volatile memory can accelerate the neural-network training algorithm known as backpropagation by performing parallelized multiply-accumulate operations in the analogue domain at the location of the weight data. However, the classification accuracies of such in situ training using non-volatile-memory hardware have generally been less than those of software-based training, owing to insufficient dynamic range and excessive weight-update asymmetry. Here we demonstrate mixed hardware-software neural-network implementations that involve up to 204,900 synapses and that combine long-term storage in phase-change memory, near-linear updates of volatile capacitors and weight-data transfer with 'polarity inversion' to cancel out inherent device-to-device variations. We achieve generalization accuracies (on previously unseen data) equivalent to those of software-based training on various commonly used machine-learning test datasets (MNIST, MNIST-backrand, CIFAR-10 and CIFAR-100). The computational energy efficiency of 28,065 billion operations per second per watt and throughput per area of 3.6 trillion operations per second per square millimetre that we calculate for our implementation exceed those of today's graphical processing units by two orders of magnitude. This work provides a path towards hardware accelerators that are both fast and energy efficient, particularly on fully connected neural-network layers.

Equivalent-accuracy accelerated neural-network training using analogue memory

The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. >

A 10-b 50-MHz digital-to-analog (D/A) converter for video applications that is based on a dual-ladder resistor string is presented. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces the glitch energy, and signal-dependent switch signals reduce high-frequency distortion. The output buffer allows driving 1 V/sub pp/ to 75 Omega . The chip consumes 65 mW at maximum clock frequency and a full-swing output signal. The device is processed in a standard 1.6- mu m CMOS process with a single 5-V supply voltage. The double-ladder architecture allows the requirements for small cell area and high linearity to be separated. Compensation techniques have been applied to reduce the second- and third-order distortion components; at 5-MHz signal frequency the total harmonic distortion is -53 dB. >

A 10-b 50-MHz CMOS D/A converter with 75- Omega buffer

A digital-to-analog converter (DAC) has been designed which uses an algorithm based on interpolation. The algorithm ensures monotonicity and differential linearity despite offset voltages, and hence eliminates the need for trimming. The technique has been used to design a 15-bit DAC in a 2.5- mu m CMOS technology. The converter features S/(N+THD) of 74 dB with a dynamic range of 87 dB and a power consumption of 22 mW at 44-kHz sample frequency. >

An algorithmic 15-bit CMOS digital-to-analog converter

A chip that performs and evaluates a 16/spl times/16-pixel comparison for application in pattern recognition systems is described. The on-chip data organization and the Wallace-tree evaluation circuits are described. The chip has been realized in a 2-/spl mu/m NMOS process and operated at 18 MHz, thus performing four gigapixel operations per second.

FEBRIS: a chip for pattern recognition

This article presents a fully dynamic latched comparator with a high-gain three-stage configuration and an extra parallel feed-forward path, able to achieve a delay of 26.8 ps and a data rate of 13.5 Gb/s with less than 10−12 BER for a 5 <inline-formula> <tex-math notation="LaTeX">$\text{m}\text {V}_{\text {pp}}$ </tex-math></inline-formula> differential input (<inline-formula> <tex-math notation="LaTeX">$\Delta V_{\textrm {I}}$ </tex-math></inline-formula>) at 0.5 V common-mode (<inline-formula> <tex-math notation="LaTeX">$V_{\textrm {CM}}$ </tex-math></inline-formula>) and 1V supply (<inline-formula> <tex-math notation="LaTeX">$V_{\textrm {DD}}$ </tex-math></inline-formula>). Additionally, the reduced-stacking cascaded triple-latch arrangement enables a < 70ps delay down to 0.6 V <inline-formula> <tex-math notation="LaTeX">$V_{\textrm {DD}}$ </tex-math></inline-formula>. The comparator is analyzed and compared against two prior art circuits by means of derived delay and noise expressions, serving as design guidelines. The prototype comparator and its prior art are fabricated in 28 nm bulk CMOS, with delay, input-referred noise, energy/comparison, and area measurements highlighting the benefits and trade-offs of the proposed solution.

M.J.M. Pelgrom

Papers

Matching properties of MOS transistors

A 10-b 50-MHz CMOS D/A converter with 75- Omega buffer

An algorithmic 15-bit CMOS digital-to-analog converter

FEBRIS: a chip for pattern recognition

A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity