Journal ArticleDOI
Matching properties of MOS transistors
TLDR
In this paper, the matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on several basic circuits.Abstract:
The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. >read more
Citations
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Journal ArticleDOI
Neuromorphic Silicon Neuron Circuits
Giacomo Indiveri,Bernabe Linares-Barranco,Tara Julia Hamilton,André van Schaik,Ralph Etienne-Cummings,Tobi Delbruck,Shih-Chii Liu,Piotr Dudek,Philipp Hafliger,Sylvie Renaud,Johannes Schemmel,Gert Cauwenberghs,John V. Arthur,Kai Hynna,Fopefolu Folowosele,Sylvain Saïghi,Teresa Serrano-Gotarredona,Jayawan H B Wijekoon,Yingxue Wang,Kwabena Boahen +19 more
TL;DR: The most common building blocks and techniques used to implement these circuits, and an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models.
Journal ArticleDOI
Matching properties of MOS transistors
TL;DR: In this article, the matching properties of the threshold voltage, substrate factor and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on a band-gap reference circuit.
Journal ArticleDOI
Timepix, a 65k programmable pixel readout chip for arrival time, energy and/or photon counting measurements
TL;DR: In this paper, the authors proposed a novel approach for the readout of a TPC at the future linear collider is to use a CMOS pixel detector combined with some kind of gas gain grid.
Journal ArticleDOI
A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line
TL;DR: Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.
Journal ArticleDOI
Equivalent-accuracy accelerated neural-network training using analogue memory
Stefano Ambrogio,Pritish Narayanan,Hsinyu Tsai,Robert M. Shelby,Irem Boybat,Irem Boybat,Carmelo di Nolfo,Carmelo di Nolfo,Severin Sidler,Severin Sidler,Massimo Giordano,Martina Bodini,Martina Bodini,Nathan C. P. Farinha,Benjamin Killeen,Christina Cheng,Yassine Jaoudi,Geoffrey W. Burr +17 more
TL;DR: Mixed hardware–software neural-network implementations that involve up to 204,900 synapses and that combine long-term storage in phase-change memory, near-linear updates of volatile capacitors and weight-data transfer with ‘polarity inversion’ to cancel out inherent device-to-device variations are demonstrated.
References
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Journal ArticleDOI
Characterisation and modeling of mismatch in MOS transistors for precision analog design
TL;DR: In this paper, a characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data and the physical causes of mismatch are discussed in detail for both p- and n-channel devices.
Journal ArticleDOI
Random error effects in matched MOS capacitors and current sources
TL;DR: Results indicate that a 9-bit matching accuracy can be obtained for capacitors and an 8-bit accuracy for MOS current sources without difficulty if the systematic error sources are reduced using proper design and layout techniques.
Book
Introduction to Robust and Quasi-Robust Statistical Methods
TL;DR: In this paper, the authors present a framework for robustness, breakdown point, and influence function for probability distributions. But they do not consider the effect of variance on robustness.
Journal ArticleDOI
Random errors in MOS capacitors
J.-B. Shyu,Gabor C. Temes,K. Yao +2 more
TL;DR: In this paper, the effects of random edge variations and deviations of oxide thickness and permittivity are examined, and it is shown that edge effects introduce a relative capacitance error /spl Delta C/C/spl alpha C/SUP -3/4/, while the oxide variations cause /spl C/c/spl α C/ SUP -1/2/.
Journal ArticleDOI
Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter
TL;DR: Standard process CMOS/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A/D converter that may be interconnected in series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates.