M
M. Jagadesh Kumar
Researcher at Indian Institute of Technology Delhi
Publications - 122
Citations - 3610
M. Jagadesh Kumar is an academic researcher from Indian Institute of Technology Delhi. The author has contributed to research in topics: Bipolar junction transistor & Field-effect transistor. The author has an hindex of 29, co-authored 122 publications receiving 3126 citations. Previous affiliations of M. Jagadesh Kumar include Indian Institute of Technology Madras & Indian Institute of Technology Kharagpur.
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Doping-Less Tunnel Field Effect Transistor: Design and Investigation
TL;DR: In this article, a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept was performed using calibrated simulations.
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Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain
TL;DR: In this article, the authors demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET).
Journal ArticleDOI
Investigation of the Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field Effect Transistor
Sneh Saurabh,M. Jagadesh Kumar +1 more
TL;DR: In this article, a dual material gate (DMG) was applied to a tunnel field effect transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average sub-threshold slope.
Posted Content
A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET - Two-dimensional Analytical Modeling and Simulation
TL;DR: In this paper, the authors presented the unique features exhibited by modified asymmetrical double gate (DG) silicon on insulator (SOI) MOSFET, which exhibits significantly reduced short channel effects.
Posted Content
Bipolar Charge Plasma Transistor: A Novel Three Terminal Device
M. Jagadesh Kumar,Kanika Nadda +1 more
TL;DR: In this article, a novel approach for forming a lateral Bipolar Charge Plasma Transistor (BCPT) is explored using 2D simulations using different metal work function electrodes to induce n-and p-type charge plasma layers on undoped SOI to form the emitter, base and collector regions of a lateral NPN transistor.