Traditional von Neumann computing systems involve separate processing and memory units. However, data movement is costly in terms of time and energy and this problem is aggravated by the recent explosive growth in highly data-centric applications related to artificial intelligence. This calls for a radical departure from the traditional systems and one such non-von Neumann computational approach is in-memory computing. Hereby certain computational tasks are performed in place in the memory itself by exploiting the physical attributes of the memory devices. Both charge-based and resistance-based memory devices are being explored for in-memory computing. In this Review, we provide a broad overview of the key computational primitives enabled by these memory devices as well as their applications spanning scientific computing, signal processing, optimization, machine learning, deep learning and stochastic computing. This Review provides an overview of memory devices and the key computational primitives for in-memory computing, and examines the possibilities of applying this computing approach to a wide range of applications.

Memory devices and applications for in-memory computing

More particularly, calculations are developed and examined to reduce the entire quantity of Wireless access points as well as their locations in almost any given atmosphere while with the throughput needs and the necessity to ensure every place in the area can achieve a minimum of k APs. This paper concentrates on using Wireless for interacting with and localizing the robot. We've carried out thorough studies of Wireless signal propagation qualities both in indoor and outside conditions, which forms the foundation for Wireless AP deployment and communication to be able to augment how human operators communicate with this atmosphere, a mobile automatic platform is developed. Gas and oil refineries could be a harmful atmosphere for various reasons, including heat, toxic gasses, and unpredicted catastrophic failures. When multiple Wireless APs are close together, there's a possible for interference. A graph-coloring heuristic can be used to find out AP funnel allocation. Additionally, Wireless fingerprinting based localization is developed. All of the calculations implemented are examined in real life situations using the robot developed and answers are promising. For example, within the gas and oil industry, during inspection, maintenance, or repair of facilities inside a refinery, people might be uncovered to seriously high temps to have a long time, to toxic gasses including methane and H2S, and also to unpredicted catastrophic failures.

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Internet of Vehicles: From Intelligent Grid to Autonomous Cars and Vehicular Clouds

A crossbar array of magnetoresistive memory devices for in-memory computing

This article presents C3SRAM, an in-memory-computing SRAM macro. The macro is an SRAM module with the circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations. The macro utilizes analog-mixed-signal (AMS) capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without the need to access the stored weights by individual row, the macro asserts all its rows simultaneously and forms an analog voltage at the read bitline node through capacitive voltage division. With one analog-to-digital converter (ADC) per column, the macro realizes fully parallel vector–matrix multiplication in a single cycle. The network type that the macro supports and the computing mechanism it utilizes are determined by the robustness and error tolerance necessary in AMS computing. The C3SRAM macro is prototyped in a 65-nm CMOS. It demonstrates an energy efficiency of 672 TOPS/W and a speed of 1638 GOPS (20.2 TOPS/mm2), achieving 3975 $\times $ better energy–delay product than the conventional digital baseline performing the same operation. The macro achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10, which is among the best in-memory computing works in terms of energy efficiency and inference accuracy tradeoff.

C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism

This book provides a structured treatment of the key principles and techniques for enabling efficient processing of deep neural networks (DNNs) DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity Therefore, techniques that enable efficient processing of deep neural networks to improve key metrics—such as energy-efficiency, throughput, and latency—without sacrificing accuracy or increasing hardware costs are critical to enabling the wide deployment of DNNs in AI systems The book includes background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies Readers will find a structured introduction to the field as well as formalization and organization of key concepts from contemporary work that provide insights that may spark new ideas

Efficient Processing of Deep Neural Networks

High-dimensionality matrix-vector multiplication (MVM) is a dominant kernel in signal-processing and machine-learning computations that are being deployed in a range of energy- and throughput-constrained applications. In-memory computing (IMC) exploits the structural alignment between a dense 2D array of bit cells and the dataflow in MVM, enabling opportunities to address computational energy and throughput. Recent prototypes have demonstrated the potential for 10 t benefits in both metrics. However, fitting computation within an array of constrained bit-cell circuits imposes a number of challenges, including the need for analog computation, efficient interfacing with conventional digital accelerators (enabling the required programmability), and efficient virtualization of the hardware to map software. This article provides an overview of the fundamentals of IMC to better explain these challenges and then identifies promising paths forward among the wide range of emerging research.

In-Memory Computing: Advances and prospects

This paper presents a scalable neural-network (NN) inference accelerator in 16nm, based on an array of programmable cores employing mixed-signal In-Memory Computing (IMC), digital Near-Memory Computing (NMC), and localized buffering/control. IMC achieves high energy efficiency and throughput for matrix-vector multiplications (MVMs), which dominate NNs; but, scalability poses numerous challenges, both technologically, going to advanced nodes to maintain gains over digital architectures, and architecturally, for full execution of diverse NNs. Recent demonstrations have explored integrating IMC in programmable processors [1, 2], but have not achieved IMC efficiency and throughput for full executions. The central challenge is drastically different physical design points and associated tradeoffs incurred by IMC compared to digital engines. Namely, IMC substantially increases compute energy efficiency and HW density/parallelism, but retains the overheads of HW virtualization (state and data swapping/buffering/communication across spatial/temporal computation mappings). The demonstrated architecture is co-designed with SW-mapping algorithms (encapsulated in a custom graph compiler), to provide efficiency across a broad range of mapping strategies, to overcome these overheads.

A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

This letter presents a system that enables identification and localization of objects through an array of RFID-readers integrated into a thin sheet via large-area electronics, for lining everyday surfaces. We demonstrate a 5 ${\times }$ 5 active matrix of RFID readers based on thin-film transistor (TFT) LC oscillators, using in-house fabricated ZnO TFTs. The array is designed to read commercial ISO14443 13.56 MHz tags, employing a tag-talks-first protocol to maximize readout speed for high array frame rate. The spatial resolution is set by the reader coil dimensions, which are 3.7 cm ${\times }$ 3.7 cm, for a maximum of 730 pixels/m2. Using a 2.4 cm ${\times }$ 2.4 cm tag the array achieves a vertical read range of 3 cm and lateral range of 1.6 cm at a readout speed of 5 ms per element (set by the commercial tag). Readout is accomplished by sensing the current via the shared VDD line of the array, in order to reduce interfacing requirements as array size scales. After filtering and amplification, the demodulated data has an amplitude of >350 mV and the maximum power consumed by the reader array is <280 mW.

Large-Area Electronics HF RFID Reader Array for Object-Detecting Smart Surfaces

The tremendous value artificial intelligence (AI) is showing across a broad range of applications is driving it from cyber-systems to systems pervading every aspect of our lives. But real-world data challenges the efficiency and robustness with which AI systems of today can perform, due to the highly dynamic and noisy scenarios they face. While algorithmic solutions are required, this paper also explores technological solutions based on large-scale sensing. Specifically, Large-Area Electronics (LAE) is a technology that can make large-scale, form-fitting sensors possible for broad deployment in our lives. System-design principles, architectural approaches, supporting circuits, and underlying technological concerns surrounding LAE and its use in emerging systems for intelligent sensing are explored.

Artificial intelligence meets large-scale sensing: Using Large-Area Electronics (LAE) to enable intelligent spaces

Structure in data can be leveraged to enhance learning. In many perception tasks, the embedded signals arising from physical processes of interest naturally have structure of high semantic relevance. However, traditional forms of remote sensing (e.g., vision) preserve such structure only in limited ways. This paper examines how embedded, form-fitting sensing, referred to as physically integrated (PI) sensing, can preserve such structure in richer ways. While the analysis is agnostic to the particular technology for PI sensing, for which a range of options is emerging, especially driven by the Internet of Things, a particular emerging technology called large-area electronics (LAE) is considered. Using synthetic data from 3-D modeling and rendering of human-activity scenes, LAE-based PI sensing and vision-based remote sensing are emulated and perception systems are formed, showing: 1) enhanced data-efficiency of learning models based on PI sensing; 2) potential for selective deployment of PI sensors in new perception tasks, thanks to robust ranking of their value in such tasks; 3) enhanced data-efficiency of learning models based on vision sensing, by integrating PI sensing; and 4) efficient mapping of PI-sensing features across perception tasks to enhance transferability of learning.

Murat Ozatay

Papers

In-Memory Computing: Advances and prospects

A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

Large-Area Electronics HF RFID Reader Array for Object-Detecting Smart Surfaces

Artificial intelligence meets large-scale sensing: Using Large-Area Electronics (LAE) to enable intelligent spaces

Exploiting Emerging Sensing Technologies Toward Structure in Data for Enhancing Perception in Human-Centric Applications