Figures of merit connecting processing capabilities with power dissipated (OpS/Watt, Joule/bit, etc.) are becoming dominant factors in choosing technologies for implementing the next generation of computing and communication network systems. Superconductivity is viewed as a technology capable of achieving higher energy efficiencies than other technologies. Static power dissipation of standard RSFQ logic, associated with dc bias resistors, is responsible for most of the circuit power dissipation. In this paper, we review and compare different superconductor digital technology approaches and logic families addressing this problem. We present a novel energy-efficient single flux quantum logic family, ERSFQ/eSFQ. We also discuss energy-efficient approaches for output data interface and overall cryosystem design.

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Energy-Efficient Single Flux Quantum Technology

Large-scale computing system characteristics vary by application class, but power and energy use has become a major problem for all classes. Superconducting computing may be able to serve the needs of these systems significantly better than conventional technology. Recent developments in single flux quantum circuit technology for digital logic include variants with greatly improved energy efficiency. Concepts were investigated for computing systems capable of performance in the range from 1 to 1000 PFLOP/s. The concept systems were constrained to use existing commercial cryogenic refrigerators and Nb superconducting technology. In order to meet the performance goals, cache and main memory capable of operating at cryogenic temperatures will be required. Superconducting computing is shown to be potentially competitive on the basis of power and energy efficiency if key component technologies can meet specific goals. Potential advantages of superconducting computing are identified as well as areas requiring further development.

Energy-Efficient Superconducting Computing—Power Budgets and Requirements

We have developed a Josephson 4-Kbit RAM with improved component circuits and a device structure having two Nb wiring layers. A resistor coupled driver and sense circuit are improved to have wide operating margins. The fabrication process is simplified using bias sputtering, as a result, its reliability is increased. The RAM is composed of approximately 21000 Nb/AlO/sub x//Nb Josephson junctions, Mo resistors, Nb wirings, and SiO/sub 2/ insulators. Experimental results show a minimum access time of 380 ps and power dissipation of 9.5 mW. Maximum bit yield of 84% is obtained in minimum magnetic field of about 20 /spl mu/G. We confirm that most of fail bits are caused by trapped magnetic flux, and the RAM functions properly for 98% of the memory cells after measuring fail bit map several times. >

A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield

A data collection and distribution system for monitoring aircraft in flight, on the ground and at the gate or terminal for monitoring critical and catastrophic events, managing the emergency during such an event, and for investigating the event. The system generates, transmits and collects critical data generated by monitoring equipment onboard an aircraft or other commercial transport and selectively displays the data on a cockpit display console as well as for downloading, transmitting and displaying data at external monitoring and response stations, including fixed ground stations, roving ground stations and chase aircraft or vehicles. Digital surveillance information is collected, processed, dispatched, and log via remote control and access. The system includes a variety of system appliances such as surveillance cameras, sensors, detectors, and panic buttons and accommodates legacy equipment. Within the commercial transport, the system maybe hardwired or may use wireless transmission and receiving systems.

Comprehensive multi-media surveillance and response system for aircraft, operations centers, airports and other commercial transports, centers and terminals

To expand designable circuit scale, we have developed a new cell-based circuit design for single flux quantum (SFQ) circuit. We call it CONNECT cell library. The CONNECT cell library has over 100 cells at present. Each CONNECT cell consists of a Verilog digital behavior model, circuit information, and a physical layout. All circuit parameter values have been optimized for obtaining the widest margins and minimizing interactions between cells. At the layout level, we have defined a minimum standard cell size and made cell height and width a multiple of the size. Using this cell library, we can easily expand circuit scale without the time-consuming dynamic simulations of whole circuits. For estimation of the reliability of the library, we designed and fabricated test circuits using CONNECT cells. We demonstrated experimentally correct operations, which means the CONNECT cell library is sufficiently reliable.

A single flux quantum standard logic cell library

A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm 2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5 kA/cm 2 to 10 kA/cm 2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400 GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz.

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100 GHz demonstrations based on the single-flux-quantum cell library for the 10 kA/cm 2 Nb multi-layer process

A Josephson 256-word/spl times/16-bit RAM that includes a power circuit has been developed to enable high-frequency clock operation. This RAM consists of a 4/spl times/4 matrix array of 256 RAM blocks, impedance-matched lines, and signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned up to a clock frequency of 1.07 GHz. We succeeded in feeding a large high-frequency current of more than 2 A into the entire 256-word/spl times/16-bit RAM. The 256-word/spl times/16-bit RAM therefore functioned up to a clock frequency of 620 MHz.

High-frequency clock operation of Josephson 256-word/spl times/16-bit RAMs

A fully decoded 4-kb Josephson nondestructive readout high-speed RAM with vortex transitional memory cells was designed and operated successfully. The 4-kb Josephson RAM is composed of 64-b*64-b cells, polarity-convertible drivers, address decoders using resistor coupled Josephson logic (RCJL) gates, and a resistively loaded sense circuit. The memory cells use vortex transitions in their superconducting loops for writing and reading data. The cells are activated by two control signals without timing control, while all peripheral circuits are activated by an AC power supply. This memory configuration eliminates the timing sequence needed for memory operations, resulting in a decrease in the memory operation time for an actual memory chip. The 4-kb Josephson high-speed RAM was fabricated using niobium planarization technique with a 1.5- mu m design rule. The RAM circuit size is 4.8*4.8 mm/sup 2/ and the memory cell is 55*55 mu m/sup 2/. More than 25000 Nb-AlO/sub x/-Nb Josephson junctions with approximately 1200 A/cm/sup 2/ critical current density are contained in the RAM chip. An access time of 580 ps and a power consumption of 6.7 mW are obtained for the nondestructive memory operation.

A 4-kbit Josephson nondestructive read-out RAM operated at 580 psec and 6.7 mW

We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 1×1μm, a line width of 0.8μm, a JJ critical current density of 10kA/cm2, a 2.4Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.

Shuichi Nagasawa

Papers

A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield

100 GHz demonstrations based on the single-flux-quantum cell library for the 10 kA/cm 2 Nb multi-layer process

High-frequency clock operation of Josephson 256-word/spl times/16-bit RAMs

A 4-kbit Josephson nondestructive read-out RAM operated at 580 psec and 6.7 mW

Improvements in Fabrication Process for Nb-Based Single Flux Quantum Circuits in Japan