Electrons have a charge and a spin, but until recently these were considered separately. In classical electronics, charges are moved by electric fields to transmit information and are stored in a capacitor to save it. In magnetic recording, magnetic fields have been used to read or write the information stored on the magnetization, which 'measures' the local orientation of spins in ferromagnets. The picture started to change in 1988, when the discovery of giant magnetoresistance opened the way to efficient control of charge transport through magnetization. The recent expansion of hard-disk recording owes much to this development. We are starting to see a new paradigm where magnetization dynamics and charge currents act on each other in nanostructured artificial materials. Ultimately, 'spin currents' could even replace charge currents for the transfer and treatment of information, allowing faster, low-energy operations: spin electronics is on its way.

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The emergence of spin electronics in data storage

This review provides a theoretical basis for understanding the current-phase relation (CPhiR) for the stationary (dc) Josephson effect in various types of superconducting junctions The authors summarize recent theoretical developments with an emphasis on the fundamental physical mechanisms of the deviations of the CPhiR from the standard sinusoidal form A new experimental tool for measuring the CPhiR is described and its practical applications are discussed The method allows one to measure the electrical currents in Josephson junctions with a small coupling energy as compared to the thermal energy A number of examples illustrate the importance of the CPhiR measurements for both fundamental physics and applications

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The current-phase relation in Josephson junctions

In this paper, recent developments in magnetic tunnel junctions (MTJs) are reported with their potential impacts on integrated circuits. MTJs consist of two metal ferromagnets separated by a thin insulator and exhibit two resistances, low (Rp) or high (Rap) depending on the relative direction of ferromagnet magnetizations, parallel (P) or antiparallel (AP), respectively. Tunnel magnetoresistance (TMR) ratios, defined as (Rap $Rp)/Rp as high as 361%, have been obtained in MTJs with Co40Fe40B20 fixed and free layers made by sputtering with an industry-standard exchange-bias structure and post deposition annealing at Ta = 400 degC. The corresponding output voltage swing DeltaV is over 500 mV, which is five times greater than that of the conventional amorphous Al-O-barrier MTJs. The highest TMR ratio obtained so far is 500% in a pseudospin-valve MTJ annealed at Ta = 475 degC, showing a high potential of the current material system. In addition to this high-output voltage swing, current-induced magnetization switching (CIMS) takes place at the critical current densities (JCO) on the order of 106 A/cm2 in these MgO-barrier MTJs. Furthermore, high antiferromagnetic coupling between the two CoFeB layers in a synthetic ferrimagnetic free layer has been shown to result in a high thermal-stability factor with a reduced JCO compared to single free-layer MTJs. The high TMR ratio enabled by the MgO-barrier MTJs, together with the demonstration of CIMS at a low JCO, allows development of not only scalable magnetoresistive random-access memory with feature sizes below 90 nm but also new memory-in-logic CMOS circuits that can overcome a number of bottlenecks in the current integrated-circuit architecture

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Magnetic Tunnel Junctions for Spintronic Memories and Beyond

Large-scale computing system characteristics vary by application class, but power and energy use has become a major problem for all classes. Superconducting computing may be able to serve the needs of these systems significantly better than conventional technology. Recent developments in single flux quantum circuit technology for digital logic include variants with greatly improved energy efficiency. Concepts were investigated for computing systems capable of performance in the range from 1 to 1000 PFLOP/s. The concept systems were constrained to use existing commercial cryogenic refrigerators and Nb superconducting technology. In order to meet the performance goals, cache and main memory capable of operating at cryogenic temperatures will be required. Superconducting computing is shown to be potentially competitive on the basis of power and energy efficiency if key component technologies can meet specific goals. Potential advantages of superconducting computing are identified as well as areas requiring further development.

Energy-Efficient Superconducting Computing—Power Budgets and Requirements

We have developed a Josephson 4-Kbit RAM with improved component circuits and a device structure having two Nb wiring layers. A resistor coupled driver and sense circuit are improved to have wide operating margins. The fabrication process is simplified using bias sputtering, as a result, its reliability is increased. The RAM is composed of approximately 21000 Nb/AlO/sub x//Nb Josephson junctions, Mo resistors, Nb wirings, and SiO/sub 2/ insulators. Experimental results show a minimum access time of 380 ps and power dissipation of 9.5 mW. Maximum bit yield of 84% is obtained in minimum magnetic field of about 20 /spl mu/G. We confirm that most of fail bits are caused by trapped magnetic flux, and the RAM functions properly for 98% of the memory cells after measuring fail bit map several times. >

A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield

To expand designable circuit scale, we have developed a new cell-based circuit design for single flux quantum (SFQ) circuit. We call it CONNECT cell library. The CONNECT cell library has over 100 cells at present. Each CONNECT cell consists of a Verilog digital behavior model, circuit information, and a physical layout. All circuit parameter values have been optimized for obtaining the widest margins and minimizing interactions between cells. At the layout level, we have defined a minimum standard cell size and made cell height and width a multiple of the size. Using this cell library, we can easily expand circuit scale without the time-consuming dynamic simulations of whole circuits. For estimation of the reliability of the library, we designed and fabricated test circuits using CONNECT cells. We demonstrated experimentally correct operations, which means the CONNECT cell library is sufficiently reliable.

A single flux quantum standard logic cell library

This paper describes newly developed magnetic random access memory (MRAM) cell technology suitable for high-speed memory macros embedded in next-generation system LSIs: a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ, and a 5T2MTJ cell structure. The 2T1MTJ cell structure makes it possible to significantly improve the write margin and accelerate the operating speed to 200 MHz. Its high compatibility with SRAM specifications and its wide write margin were confirmed by measuring 2T1MTJ MRAM test chips. Although the cell structure requires a small-writing-current MTJ, the current can be reduced to 1mA using the newly developed write-line-inserted MTJ. Further development to reduce the current down to 0.5 mA is required to obtain a cell area of 1.9 mum2, which is smaller than the SRAM cell area, in the 0.13-mum CMOS process. The 5T2MTJ cell structure also enables random-access operation over 500 MHz because the sensing signal is amplified in each cell. Random access time of less than 2 ns can be achieved with SPICE simulation when the magnetic resistance is 5 kOmega and the magnetoresistive (MR) ratio is more than 70%

MRAM Cell Technology for Over 500-MHz SoC

This paper describes recent results on the fabrication, electrical characteristics, and microstructure of high-temperature superconducting edge-type Josephson junctions with modified interface barriers. The barriers are formed by surface modification of the YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// base layer. This process involves structural and chemical modification by ion irradiation and crystallization by annealing. The junctions showed resistively and capacitively shunted junction-like current-voltage characteristics and excellent uniformity. The spread in the critical current for one hundred junctions was smaller than 1/spl sigma/=10% at 4.2 K. The uniformity is now approaching 1/spl sigma/=5%. The junction characteristics have remained the same after two-year room-temperature storage. They also showed no change after high-temperature processing at about 700/spl deg/C. High-resolution transmission electron microscopy revealed that both the crystal structure and chemical composition in relatively thick barriers are different from those of YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta//.

High-temperature superconducting edge-type Josephson junctions with modified interface barriers

An integration process for the fabrication of an all refractory Josephson LSI logic circuit is described. In this process, niobium nitride and niobium double-layered Josephson junctions were integrated using a reactive ion etching with a 2.5 μm minimum feature. A highly selective and anisotropic RIE process and a planarizing technology have been developed for intagrating a circuit with LSI complexity. For evaluating the process capability, test vehicle circuits with MSI/LSI level complexity have been designed and fabricated using this process. An 8 bit ripple carry adder and a 4×4 bit parallel multiplier have been integrated with Josephson four junction logic ( 4JL ) gates, the largest of which contains more than 2800 Josephson junctions. Both functionality and high-speed performance testings have been successfully performed with these test circuits.

Shuichi Tahara

Papers

A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield

A single flux quantum standard logic cell library

MRAM Cell Technology for Over 500-MHz SoC

High-temperature superconducting edge-type Josephson junctions with modified interface barriers

An integration of all refractory Josephson logic LSI circuit