T
Tushar Krishna
Researcher at Massachusetts Institute of Technology
Publications - 63
Citations - 8010
Tushar Krishna is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Computer science & Network on a chip. The author has an hindex of 19, co-authored 29 publications receiving 6728 citations. Previous affiliations of Tushar Krishna include Indian Institutes of Technology & Princeton University.
Papers
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Journal ArticleDOI
The gem5 simulator
Nathan Binkert,Bradford M. Beckmann,Gabriel Black,Steven K. Reinhardt,Ali G. Saidi,Arkaprava Basu,Joel Hestness,Derek R. Hower,Tushar Krishna,Somayeh Sardashti,Rathijit Sen,Korey Sewell,Muhammad Shoaib,Nilay Vaish,Mark D. Hill,Darien Wood +15 more
TL;DR: The high level of collaboration on the gem5 project, combined with the previous success of the component parts and a liberal BSD-like license, make gem5 a valuable full-system simulation tool.
Journal ArticleDOI
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
TL;DR: Eyeriss as mentioned in this paper is an accelerator for state-of-the-art deep convolutional neural networks (CNNs) that optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, by reconfiguring the architecture.
Proceedings ArticleDOI
GARNET: A detailed on-chip network model inside a full-system simulator
TL;DR: In this article, a detailed cycle-accurate interconnection network model (GARNET) is proposed to simulate a CMP architecture with virtual channel (VC) flow control.
Journal ArticleDOI
SCORPIO: a 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering
Bhavya K. Daya,Chia-Hsin Owen Chen,Suvinay Subramanian,Woo-Cheol Kwon,Sunghyun Park,Tushar Krishna,Jim Holt,Anantha P. Chandrakasan,Li-Shiuan Peh +8 more
TL;DR: SCORPIO is presented, an ordered mesh Network-on-Chip (NoC) architecture with a separate fixed-latency, bufferless network to achieve distributed global ordering, designed to plug-and-play with existing multicore IP and with practicality, timing, area, and power as top concerns.
Proceedings ArticleDOI
Breaking the on-chip latency barrier using SMART
TL;DR: This work proposes an on-chip network called SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) that aims to present a single-cycle data-path all the way from the source to the destination.