Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/ ${{\mu }}$ m. A common approach to TFET characterization is proposed to facilitate future comparisons.

Tunnel Field-Effect Transistors: State-of-the-Art

Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the complementary metal-oxide-semiconductor (CMOS) roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time, and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.

Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Tunnel Field-Effect Transistors: Prospects and Challenges

A new benchmarking of beyond-CMOS exploratory devices for logic integrated circuits is presented. It includes new devices with ferroelectric, straintronic, and orbitronic computational state variables. Standby power treatment and memory circuits are included. The set of circuits is extended to sequential logic, including arithmetic logic units. The conclusion that tunneling field-effect transistors are the leading low-power option is reinforced. Ferroelectric transistors may present an attractive option with faster switching delay. Magnetoelectric effects are more energy efficient than spin transfer torque, but the switching speed of magnetization is a limitation. This article enables a better focus on promising beyond-CMOS exploratory devices.

Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Quantum engineering of transistors based on 2D materials heterostructures

Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can be used at the front end of line or at the back end of line through monolithic or heterogeneous integration remains to be determined. To achieve this, multiple challenges must be overcome, including reducing the contact resistance, developing stable and controllable doping schemes, advancing mobility engineering and improving high-κ dielectric integration. The large-area growth of uniform 2D layers is also required to ensure low defect density, low device-to-device variation and clean interfaces. Here we review the development of 2D field-effect transistors for use in future VLSI technologies. We consider the key performance indicators for aggressively scaled 2D transistors and discuss how these should be extracted and reported. We also highlight potential applications of 2D transistors in conventional micro/nanoelectronics, neuromorphic computing, advanced sensing, data storage and future interconnect technologies. This Review examines the development of field-effect transistors based on two-dimensional materials and considers the challenges that need to be addressed for the devices to be incorporated into very large-scale integration (VLSI) technology.

Transistors based on two-dimensional materials for future integrated circuits

A detailed circuit assessment of Tunneling Field Effect Transistors (TFET) versus MOSFET operating near device threshold supply voltage, including the consideration of process variations, is reported. The analysis incorporates simulated 20nm TFET and MOSFET device characteristics combined with detailed circuit simulation. For very low power logic applications requiring near device threshold supply voltage, the results show that TFET logic can operate at equal standby power and switching energy to MOSFET, but with a ∼8x performance advantage. The study also shows that device parameter variation is not a significant factor for differentiation between MOSFET and TFET.

Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic

The Tunneling Field Effect Transistor (TFET) is of interest for future low-power technologies due to its steep subthreshold-slope (SS) [1, 2]. In addition to understanding TFET's prospects for future technology nodes [3], we also need to assess if it enables continued scaling required for increasing transistor density. GaSb/InAs heterojunction TFET (Het-j TFET) is one of the leading TFET options due to its high drive-current [4]. In this paper, double-gate (DG) and nanowire (NW) Het-j TFETs (Fig. 1) are atomisticly modeled and compared to a MOSFET down to Lg~9nm, i.e. ITRS 2022 node [5]. To achieve TFET characteristics superior to a MOSFET, its DG body has to be extremely thin, so a NW TFET is therefore preferred due to its more relaxed thickness and better transistor characteristics. A new device - the Resonant-TFET (R-TFET), is proposed, with SS~25mV/dec over ~3.5 decades of current, enabling the scaling of tunneling transistors to sub-9nm gate-lengths (Lg).

Heterojunction TFET Scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length

A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy. Retention of a minimum 3-muA sensing window for 100 ms, in devices with 60-nm gate-length (Lg) and 70-nm diffusion width (W), represents the best retention time of all sub-100-nm FBC devices. FBC scaling is predicted to be feasible at least to 40-nm Lg, enabling memory cell sizes much smaller than 6T-SRAM at 16-nm technology node. Functional 32-nm Lg devices suggest the feasibility at the 11-nm technology node.

Uygar E. Avci

Papers

Tunnel Field-Effect Transistors: Prospects and Challenges

Transistors based on two-dimensional materials for future integrated circuits

Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic

Heterojunction TFET Scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length

A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond