Tunnel Field-Effect Transistors: Prospects and Challenges
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TLDR
The tunnel field effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage as mentioned in this paper.Abstract:
The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.read more
Citations
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Journal ArticleDOI
Symmetric U-Shaped Gate Tunnel Field-Effect Transistor
TL;DR: In this paper, a novel heterojunction symmetric U-shaped gate tunnel FET (SUTFET) is proposed and investigated by Silvaco Atlas simulation, which can enlarge the area of the tunneling junction and facilitate the implementation of a smaller device area.
Journal ArticleDOI
Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis
Shelly Garg,Sneh Saurabh +1 more
TL;DR: In this paper, the authors investigated the impact of a drain pocket adjacent to the drain region in tunnel field effect transistors (TFETs) to effectively suppress the ambipolar current.
Journal ArticleDOI
Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain
TL;DR: In this article, a mixed TFET-MOSFET level shifter (LS) for voltage up-conversion from the ultralow-voltage regime is proposed.
Journal ArticleDOI
Surface Potential and Drain Current Analytical Model of Gate All Around Triple Metal TFET
Navjeet Bagga,Sudeb Dasgupta +1 more
TL;DR: In this article, the impact of triple metal with unalike work functions on the gate all around (GAA) tunnel FET is studied for the first time, by using Poisson's equation and Kane's model.
Journal ArticleDOI
Miniaturization of CMOS.
Henry H. Radamson,Henry H. Radamson,Xiaobin He,Qingzhu Zhang,Jinbiao Liu,Hushan Cui,Jinjuan Xiang,Zhenzhen Kong,Wenjuan Xiong,Junjie Li,Jianfeng Gao,Hong Yang,Shihai Gu,Xuewei Zhao,Xuewei Zhao,Yong Du,Jiahan Yu,Guilei Wang +17 more
TL;DR: This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy.
References
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Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Tunnel field-effect transistor without gate-drain overlap
TL;DR: In this article, the authors generalized the tunnel field effect transistor configuration by allowing a shorter gate structure, which is especially attractive for vertical nanowire-based transistors, and demonstrated with device simulations that the more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.
Proceedings ArticleDOI
Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing
G. Dewey,Benjamin Chu-Kung,J. Boardman,J. M. Fastenau,Jack Portland Kavalieros,Roza Kotlyar,W. K. Liu,D. Lubyshev,Matthew V. Metz,Niloy Mukherjee,P. Oakey,Ravi Pillarisetty,Marko Radosavljevic,Han Wui Then,R. Chau +14 more
TL;DR: In this paper, the steepest sub-threshold swing (SS < 60mV/decade) was achieved in a III-V TFET by using thin gate oxide, heterojunction engineering and high source doping.
Journal ArticleDOI
Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design
TL;DR: In this article, three different carbon nanotube (CN) field effect transistor (CNFET) designs are compared by simulation and experiment, and the authors explore the possibility of using CNs as gate-controlled tunneling devices.
Journal ArticleDOI
Simulation of nanowire tunneling transistors: From the Wentzel–Kramers–Brillouin approximation to full-band phonon-assisted tunneling
Mathieu Luisier,Gerhard Klimeck +1 more
TL;DR: In this paper, the Wentzel-Kramers-Brillouin (WKB) approximation and an atomistic, full-band quantum transport solver including direct and phonon-assisted tunneling (PAT) were used to simulate field effect transistors (TFETs).