Journal ArticleDOI
An evolvable hardware system in Xilinx Virtex II Pro FPGA
Zdenek Vasicek,Lukas Sekanina +1 more
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A new circuit architecture for image filter evolution is proposed based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs).Abstract:
In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs). Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution by Martinek and Sekanina, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 sec in average.read more
Citations
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Journal ArticleDOI
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing
TL;DR: The evolvable hardware system, fully contained in an FPGA, which is capable of autonomously generating digital processing circuits, implemented on an array of processing elements (PEs) is presented, a step toward fully autonomous, adaptive systems.
Proceedings ArticleDOI
Towards evolvable systems based on the Xilinx Zynq platform
Roland Dobai,Lukas Sekanina +1 more
TL;DR: Several scenarios are described of how to implement evolvable systems on a developmental board equipped with this programmable SoC and the resulting observations should be useful for those who are going to develop real-world evolable systems on the Zynq-7000 AP SoC platform.
Journal ArticleDOI
Edge-Directed Hardware Architecture for Real-Time Disparity Map Computation
TL;DR: A disparity map computation architecture targeting embedded stereo vision applications with hard real-time requirements that integrates a hardware edge detection mechanism that reduces the search space, improving the overall performance, and is configurable in terms of various application parameters, making it suitable for a number of application environments.
Book ChapterDOI
Hardware accelerators for Cartesian genetic programming
Zdenek Vasicek,Lukas Sekanina +1 more
TL;DR: A new class of FPGA-based accelerators for Cartesian Genetic Programming (CGP) contains a genetic engine which is reused in all applications and a significant speedup of evolution was obtained in comparison with a highly optimized software implementation of CGP.
Book ChapterDOI
Image Processing and CGP
TL;DR: This chapter presents three applications in which CGP can automatically generate novel image processing algorithms that compare to or exceed the best known conventional solutions.
References
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Book
Image Processing: Analysis and Machine Vision
TL;DR: The digitized image and its properties are studied, including shape representation and description, and linear discrete image transforms, and texture analysis.
Journal ArticleDOI
Explorations in design space: unconventional electronics design through artificial evolution
TL;DR: Three hypotheses are formulated: in the "design space" of possible electronic circuits, conventional design methods work within constrained regions, never considering most of the whole, but evolutionary algorithms can explore some of the regions beyond the scope of contentional methods, raising the possibility that better designs can be found.
Book ChapterDOI
A Self-reconfiguring Platform
TL;DR: In this article, a self-reconfiguring platform for FPGAs to dynamically reconfigure itself under the control of an embedded microprocessor has been reported and implemented on Xilinx Virtex IItm and Virtex II Protm devices.
Proceedings Article
Evolving hardware with genetic learning: a first step towards building a Darwin machine
Book ChapterDOI
EVOLVABLE HARDWARE Genetic Programming of a Darwin Machine
TL;DR: This paper suggests there are at least two approaches to be taken to build Darwin Machines, and suggests the first approach uses “software configurable hardware” chips, e.g. FPGAs, HDPLDs, or possibly a new generation of chips based on the ideas that FPGA etc embody.