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Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures

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TLDR
In this paper, a detailed understanding of the device physics at deep-cryogenic temperatures was developed based on a compact model based on MOS11 and PSP, and the accuracy and validity of the compact models were demonstrated by comparing time and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.
Abstract
Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16- $\mu \text{m}$ and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.

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Journal ArticleDOI

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

TL;DR: In this article, a temperature-dependent limit for the subthreshold swing in MOSFETs that deviates from the Boltzmann limit at deep-cryogenic temperatures was derived.
Posted Content

Scaling silicon-based quantum computing using CMOS technology: State-of-the-art, Challenges and Perspectives

TL;DR: This article focuses on the analysis of the scaling prospects of quantum computing systems based on CMOS technology and shows that qubits can now be manufactured in a similar fashion to silicon field-effect transistors, opening an opportunity to leverage the know-how of the CMOS industry to address the scaling challenge.
Proceedings ArticleDOI

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics

TL;DR: The progress made on the silicon-based QC platform is reviewed, which is highly promising to meet the scale-up challenges by leveraging the semiconductor industry.
References
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Journal ArticleDOI

Quantum sensing

Abstract: "Quantum sensing" describes the use of a quantum system, quantum properties or quantum phenomena to perform a measurement of a physical quantity Historical examples of quantum sensors include magnetometers based on superconducting quantum interference devices and atomic vapors, or atomic clocks More recently, quantum sensing has become a distinct and rapidly growing branch of research within the area of quantum science and technology, with the most common platforms being spin qubits, trapped ions and flux qubits The field is expected to provide new opportunities - especially with regard to high sensitivity and precision - in applied physics and other areas of science In this review, we provide an introduction to the basic principles, methods and concepts of quantum sensing from the viewpoint of the interested experimentalist
Journal ArticleDOI

Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

TL;DR: In this article, a feed-forward noise-canceling technique is proposed to cancel the noise and distortion contributions of the matching device, which allows for designing wide-band impedance-matching amplifiers with noise figure (NF) well below 3 dB.
Journal ArticleDOI

A programmable two-qubit quantum processor in silicon

TL;DR: A two-qubit quantum processor in a silicon device is demonstrated in this paper, which can perform the Deutsch-Josza algorithm and the Grover search algorithm on demand.
Journal ArticleDOI

A quantum-dot spin qubit with coherence limited by charge noise and fidelity higher than 99.9.

TL;DR: It is revealed that the free-evolution dephasing is caused by charge noise—rather than conventional magnetic noise—as highlighted by a 1/f spectrum extended over seven decades of frequency, offering a promising route to large-scale spin-qubit systems with fault-tolerant controllability.
Journal ArticleDOI

Supply and threshold voltage scaling for low power CMOS

TL;DR: In this paper, the authors investigated the effect of reducing the supply and threshold voltage on the energy efficiency of CMOS circuits and showed that when the transistors are velocity saturated and the nodes have a high activity factor, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V.
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