R
Raoul Velazco
Researcher at University of Grenoble
Publications - 210
Citations - 4388
Raoul Velazco is an academic researcher from University of Grenoble. The author has contributed to research in topics: Fault injection & Single event upset. The author has an hindex of 30, co-authored 209 publications receiving 4133 citations. Previous affiliations of Raoul Velazco include Grenoble Institute of Technology & Centre national de la recherche scientifique.
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Journal ArticleDOI
Upset hardened memory design for submicron CMOS technology
TL;DR: In this article, a design technique for storage elements which are insensitive to radiation-induced single-event upsets is proposed for implementation in high density ASICs and static RAMs using submicron CMOS technology.
Journal Article
A Survey on Fault Injection Techniques
TL;DR: A survey on fault injection techniques with comparison of the different injection techniques and an overview on the different tools is presented.
Journal ArticleDOI
Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection
TL;DR: Experimental results, obtained on programs running on two different digital boards, built around an 80C51 microcontroller and a 320C50 Digital Signal Processor, illustrate the potentialities of this new strategy based on the injection of bit-flips randomly in time and location.
BookDOI
Radiation Effects on Embedded Systems
TL;DR: In this article, the authors provide an extensive overview of radiation effects on integrated circuits, offering major guidelines for coping with radiation effect on components, based on the tutorials presented at the International School on Effects of Radiation on Embedded Systems for Space Applications (SERESSA).
Journal ArticleDOI
Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
TL;DR: A software modification strategy allowing on-line detection of transient errors based on a set of rules for introducing redundancy in the high-level code, which is therefore particularly suited for low-cost safety-critical microprocessor-based applications.