Design of Ion-Implanted MOSFET’s with
Very Small Physical Dimensions
ROBERT H. DENNARD, MEMBER, IEEE, FRITZ H. GAENSSLEN, HWA-NIEN YU, MEMBER, IEEE
,
V. LEO RIDEOUT,
MEMBER, IEEE, ERNEST BASSOUS, AND ANDRE R. LEBLANC, MEMBER, IEEE
Classic Paper
This paper considers the design, fabrication, and characteriza-
tion of very small MOSFET switching devices suitable for digital
integrated circuits using dimensions of the order of 1
. Scaling
relationships are presented which show how a conventional MOS-
FET can be reduced in size. An improved small device structure
is presented that uses ion implantation to provide shallow source
and drain regions and a nonuniform substrate doping profile. One-
dimensional models are used to predict the substrate doping profile
and the corresponding threshold voltage versus source voltage
characteristic. A two-dimensional current transport model is used
to predict the relative degree of short-channel effects for different
device parameter combinations. Polysilicon-gate MOSFET’s with
channel lengths as short as 0.5
were fabricated, and the device
characteristics measured and compared with predicted values. The
performance improvement expected from using these very small
devices in highly miniaturized integrated circuits is projected.
I. LIST OF SYMBOLS
Inverse semilogarithmic slope of sub-
threshold characteristic.
Width of idealized step function pro-
file for channel implant.
Work function difference between
gate and substrate.
Dielectric constants for silicon and
silicon dioxide.
Drain current.
Boltzmann’s constant.
Unitless scaling constant.
MOSFET channel length.
Effective surface mobility.
Intrinsic carrier concentration.
Substrate acceptor concentration.
Band bending in silicon at the onset
of strong inversion for zero substrate
voltage.
Built-in junction potential.
This paper is reprinted from IEEE JOURNAL OF SOLID-STATE CIRCUITS,
vol. SC-9, no. 5, pp. 256–268, October 1974.
Publisher Item Identifier S 0018-9219(99)02196-9.
Charge on the electron.
Effective oxide charge.
Gate oxide thickness.
Absolute temperature.
Drain, source, gate and substrate volt-
ages.
Drain voltage relative to source.
Source voltage relative to sustrate.
Gate threshold voltage.
Source and drain depletion layer
widths.
MOSFET channel width.
II. I
NTRODUCTION
New high resolution lithographic techniques for forming
semiconductor integrated circuit patterns offer a decrease in
linewidth of five to ten times over the optical contact mask-
ing approach which is commonly used in the semiconductor
industry today. Of the new techniques, electron beam pat-
tern writing has been widely used for experimental device
fabrication [1]–[4] while X-ray lithography [5] and optical
projection printing [6] have also exhibited high-resolution
capability. Full realization of the benefits of these new high-
resolution lithographic techniques requires the development
of new device designs, technologies, and structures which
can be optimized for very small dimensions.
This paper concerns the design, fabrication, and char-
acterization of very small MOSFET switching devices
suitable for digital integrated circuits using dimensions of
the order of 1
. It is known that reducing the source-to-
drain spacing (i.e., the channel length) of an FET leads
to undesirable changes in the device characteristics. These
changes become significant when the depletion regions
surrounding the source and drain extend over a large
portion of the region in the silicon substrate under the gate
electrode. For switching applications, the most undesirable
“short-channel” effect is a reduction in the gate threshold
voltage at which the device turns on, which is aggravated
0018–9219/99$10.00 1999 IEEE
PROCEEDINGS OF THE IEEE, VOL. 87, NO. 4, APRIL 1999 668
by high drain voltages. It has been shown that these short-
channel effects can be avoided by scaling down the vertical
dimensions (e.g., gate insulator thickness, junction depth,
etc.) along with the horizontal dimensions, while also pro-
portionately decreasing the applied voltages and increasing
the substrate doping concentration [7], [8]. Applying this
scaling approach to a properly designed conventional-size
MOSFET shows that a 200-
˚
A gate insulator is required if
the channel length is to be reduced to 1
.
A major consideration of this paper is to show how
the use of ion implantation leads to an improved de-
sign for very small scaled-down MOSFET’s. First, the
ability of ion implantation to accurately introduce a low
concentration of doping atoms allows the substrate dop-
ing profile in the channel region under the gate to be
increased in a controlled manner. When combined with
a relatively lightly doped starting substrate, this channel
implant reduces the sensitivity of the threshold voltage to
changes in the source-to-substrate (“backgate”) bias. This
reduced “substrate sensitivity” can then be traded off for a
thicker gate insulator of 350-
˚
A thickness which tends to be
easier to fabricate reproducibly and reliably. Second, ion
implantation allows the formation of very shallow source
and drain regions which are more favorable with respect
to short-channel effects, while maintaining an acceptable
sheet resistance. The combination of these features in an
all-implanted design gives a switching device which can be
fabricated with a thicker gate insulator if desired, which
has well-controlled threshold characteristics, and which
has significantly reduced interelectrode capacitances (e.g.,
drain-to-gate or drain-to-substrate capacitances).
This paper begins by describing the scaling principles
which are applied to a conventional MOSFET to ob-
tain a very small device structure capable of improved
performance. Experimental verification of the scaling ap-
proach is then presented. Next, the fabrication process
for an improved scaled-down device structure using ion
implantation is described. Design considerations for this
all-implanted structure are based on two analytical tools: a
simple one-dimensional model that predicts the substrate
sensitivity for long channel-length devices, and a two-
dimensional current-transport model that predicts the device
turn-on characteristics as a function of channel length.
The predicted results from both analyses are compared
with experimental data. Using the two-dimensional sim-
ulation, the sensitivity of the design to various parameters
is shown. Then, detailed attention is given to an alternate
design, intended for zero substrate bias, which offers some
advantages with respect to threshold control. Finally, the
paper concludes with a discussion of the performance
improvements to be expected from integrated circuits that
use these very small FET’s.
III. D
EVICE SCALING
The principles of device scaling [7], [8] show in a
concise manner the general design trends to be followed
in decreasing the size and increasing the performance of
(a) (b)
Fig. 1. Illustration of device scaling principles with
=
5
.
(a) Conventional commercially available device structure. (b)
Scaled-down device structure.
MOSFET switching devices. Fig. 1 compares a state-of-
the-art n-channel MOSFET [9] with a scaled-down device
designed following the device scaling principles to be
described later. The larger structure shown in Fig. 1(a)
is reasonably typical of commercially available devices
fabricated by using conventional diffusion techniques. It
uses a 1000-
˚
A gate insulator thickness with a substrate
doping and substrate bias chosen to give a gate threshold
voltage
of approximately 2 V relative to the source
potential. A substrate doping of 5
10 cm is low
enough to give an acceptable value of substrate sensitivity.
The substrate sensitivity is an important criterion in digital
switching circuits employing source followers because the
design becomes difficult if the threshold voltage increases
by more than a factor of two over the full range of variation
of the source voltage. For the device illustrated in Fig. 1(a),
the design parameters limit the channel length
to about
5
. This restriction arises primarily from the penetration
of the depletion region surrounding the drain into the area
normally controlled by the gate electrode. For a maximum
drain voltage of approximately 12–15 V this penetration
will modify the surface potential and significantly lower
the threshold voltage.
In order to design a new device suitable for smaller
values of
, the device is scaled by a transformation in
three variables: dimension, voltage, and doping. First, all
linear dimensions are reduced by a unitless scaling factor
,
e.g.,
, where the primed parameters refer to the
new scaled-down device. This reduction includes vertical
dimensions such as gate insulator thickness, junction depth,
etc., as well as the horizontal dimensions of channel length
and width. Second, the voltages applied to the device are
reduced by the same factor (e.g.,
). Third, the
substrate doping concentration is increased, again using the
same scaling factor (i.e.,
). The design shown in
Fig. 1(b) was obtained using
which corresponds to
the desired reduction in channel length to 1
.
The scaling relationships were developed by observing
that the depletion layer widths in the scaled-down device are
reduced in proportion to the device dimensions due to the
reduced potentials and the increased doping. For example
sub
(1)
The threshold voltage at turn-on [9] is also decreased in
direct proportion to the reduced device voltages so that
DENNARD et al.: DESIGN OF ION-IMPLANTED MOSFET’S 669
the device will function properly in a circuit with reduced
voltage levels. This is shown by the threshold voltage
equation for the scaled-down device
sub
(2)
In (2) the reduction in
is primarily due to the decreased
insulator thickness,
, while the changes in the voltage
and doping terms tend to cancel out. In most cases of
interest (i.e., polysilicon gates of doping type opposite to
that of the substrate or aluminum gates on p-type substrates)
the work function difference
is of opposite sign,
and approximately cancels out
. is the band bending
in the silicon (i.e., the surface potential) at the onset of
strong inversion for zero substrate bias. It would appear
that the
terms appearing in (1) and (2) prevent exact
scaling since they remain approximately constant, actually
increasing slightly due to the increased doping since
ln . However, the fixed substrate
bias supply normally used with n-channel devices can be
adjusted so that
. Thus, by
scaling down the applied substrate bias more than the other
applied voltages, the potential drop across the source or
drain junctions, or across the depletion region under the
gate, can be reduced by
.
All of the equations that describe the MOSFET device
characteristics may be scaled as demonstrated above. For
example, the MOSFET current equation [9] given by
(3)
is seen to be reduced by a factor of
, for any given set of
applied voltages, assuming no change in mobility. Actually,
the mobility is reduced slightly due to increased impurity
scattering in the heavier doped substrate.
It is possible to generalize the scaling approach to include
electric field patterns and current density. The electric
field distribution is maintained in the scaled-down device
except for a change in scale for the spatial coordinates.
Furthermore, the electric field strength at any corresponding
point is unchanged because
. Thus, the carrier
velocity at any point is also unchanged due to scaling and,
hence, any saturation velocity effects will be similar in both
devices, neglecting microscopic differences due to the fixed
crystal lattice dimensions. From (3), since the device current
is reduced by
, the channel current per unit of channel
width
is unchanged by scaling. This is consistent with
the same sheet density of carriers (i.e., electrons per unit
gate area) moving at the same velocity. In the vicinity of
the drain the carriers will move away from the surface to
a lesser extent in the new device, due to the shallower
diffusions. Thus, the density of mobile carriers per unit
volume will be higher in the space-charge region around
the drain complementing the higher density of immobile
charge due to the heavier doped substrate. Other scaling
(a)
(b)
Fig. 2. Experimental drain voltage characteristics for (a) conven-
tional, and (b) scaled-down structures shown in Fig. 1 normalized
to
W=L
=
1
.
relationships for power density, delay time, etc., are given
in Table 1 and will be discussed in a subsequent section on
circuit performance.
In order to verify the scaling relationships, two sets of
experimental devices were fabricated with gate insulator of
1000 and 200
˚
A (i.e.,
). The measured drain voltage
characteristics of these devices, normalized to
are shown in Fig. 2. The two sets of characteristics are
quite similar when plotted with voltage and current scale
of the smaller device reduced by a factor of five, which
confirms the scaling predictions. In Fig. 2, the exact match
on the current scale is thought to be fortuitous since there
is some experimental uncertainty in the magnitude of the
channel length used to normalize the characteristics (see
Appendix). More accurate data from devices with larger
width and length dimensions on the same chip shows
an approximate reduction of ten percent in mobility for
devices with the heavier doped substrate. That the threshold
voltage also scales correctly by a factor of five is verified
in Fig. 3, which shows the experimental
versus
turn-on characteristics for the original and the scaled-down
devices. For the cases shown, the drain voltage is large
enough to cause pinchoff and the characteristics exhibit the
expected linear relationship. When projected to intercept the
gate voltage axis this linear relationship defines a threshold
voltage useful for most logic circuit design purposes.
One area in which the device characteristics fail to scale
is in the subthreshold or weak inversion region of the
turn-on characteristic. Below threshold,
is exponentially
dependent on
with an inverse semilogarithmic slope, ,
670 PROCEEDINGS OF THE IEEE, VOL. 87, NO. 4, APRIL 1999
Fig. 3. Experimental turn-on characteristics for conventional and
scaled-down devices shown in Fig. 1 normalized to
W=L
=
1
.
[10], [11] which for the scaled-down device is given by
volts
decade log
log (4)
which is the same as for the original larger device. The
parameter
is important to dynamic memory circuits
because it determines the gate voltage excursion required
to go from the low current “off” state to the high current
“on” state [11]. In an attempt to also extend the linear
scaling relationships to
one could reduce the operating
temperature in (4) (i.e.,
), but this would cause
a significant increase in the effective surface mobility [12]
and thereby invalidate the current scaling relationship of
(3). In order to design devices for operation at room
temperature and above, one must accept the fact that
the subthreshold behavior does not scale as desired. This
nonscaling property of the subthreshold characteristic is of
particular concern to miniature dynamic memory circuits
which require low source-to-drain leakage currents.
IV. I
ON-IMPLANTED DEVICE DESIGN
The scaling considerations just presented lead to the de-
vice structure with a 1-
channel length shown in Fig. 4(a).
In contrast, the corresponding improved design utilizing
the capability afforded by ion implantation is shown in
Fig. 4(b). The ion-implanted device uses an initial sub-
strate doping that is lower by about a factor of four, and
an implanted boron surface layer having a concentration
somewhat greater than the concentration used throughout
the unimplanted structure of Fig. 4(a). The concentration
and the depth of the implanted surface layer are chosen so
that this heavier doped region will be completely within the
surface depletion layer when the device is turned on with
the source grounded. Thus, when the source is biased above
ground potential, the depletion layer will extend deeper
into the lighter doped substrate, and the additional exposed
“bulk” charge will be reasonably small and will cause only
(a)
(b)
Fig. 4. Detailed cross sections for (a) scaled-down device struc-
ture, and (b) corresponding ion-implanted device structure.
a modest increase in the gate-to-source voltage required
to turn on the device. With this improvement in substrate
sensitivity the gate insulator thickness can be increased to
as much as 350
˚
A and still maintain a reasonable gate
threshold voltage as will be shown later.
Another aspect of the design philosophy is to use shallow
implanted n
regions of depth comparable to the implanted
p-type surface layer. The depletion regions under the gate
electrode at the edges of the source and drain are then
inhibited by the heavier doped surface layer, roughly pic-
tured in Fig. 4(b), for the case of a turned-off device.
The depletion regions under the source and drain extend
much further into the lighter doped substrate. With deeper
junctions these depletion regions would tend to merge in
the lighter doped material which would cause a loss of
threshold control or, in the extreme, punchthrough at high
drain voltages. However, the shallower junctions give a
more favorable electric field pattern which avoids these
effects when the substrate doping concentration is properly
chosen (i.e., when it is not too light).
The device capacitances are reduced with the ion-
implanted structure due to the increased depletion layer
width separating the source and drain from the substrate [cf.
Figs. 4(a) and 4(b)], and due to the natural self-alignment
afforded by the ion implantation process which reduces the
overlap of the polysilicon gate over the source and drain
regions. The thicker gate insulator also gives reduced gate
capacitance, but the performance benefit in this respect is
DENNARD et al.: DESIGN OF ION-IMPLANTED MOSFET’S 671
offset by the decreased gate field. To compensate for the
thicker gate oxide and the expected threshold increase, a
design objective for maximum drain voltage was set at 4
V for the ion-implanted design in Fig. 4(b), compared to 3
V for the scaled-down device of Fig. 4(a).
V. F
ABRICATION OF ION-IMPLANTED MOSFET’S
The fabrication process for the ion-implanted MOSFET’s
used in this study will now be described. A four-mask
process was used to fabricate polysilicon-gate, n-channel
MOSFET’s on a test chip which contains devices with
channel lengths ranging from 0.5 to 10
. Though the
eventual aim is to use electron-beam pattern exposure, it
was more convenient to use contact masking with high
quality master masks for process development. For this
purpose high resolution is required only for the gate pattern
which uses lines as small as 1.5
which are reduced in
the subsequent processing. The starting substrate resistivity
was 2
cm (i.e., about 7.5 10 cm ). The method of
fabrication for the thick oxide isolation between adjacent
FET’s is not described as it is not essential to the work
presented here, and because several suitable techniques are
available. Following dry thermal growth of the gate oxide,
low energy (40 keV), low dose (6.7
10 atoms/cm )B
ions were implanted into the wafers, raising the boron
doping near the silicon surface. All implantations were
performed after gate oxide growth in order to restrict
diffusion of the implanted regions.
After the channel implantation, a 3500-
˚
A thick polysili-
con layer was deposited, doped n
, and the gate regions
delineated. Next, n
source and drain regions 2000-
˚
A
deep were formed by a high energy (100 keV), high
dose (4
10 atoms/cm )As implantation through the
same 350-
˚
A oxide layer. During this step, however, the
polysilicon gate masks the channel region from the implant,
absorbing all of the As
dose incident there. The etching
process used to delineate the gates results in a sloping
sidewall which allows a slight penetration of As
ions
underneath the edges of the gates. The gate-to-drain (or
source) overlap is estimated to be of the order of 0.2
. The high temperature processing steps that follow the
implantations include 20 min at 900
C, and 11 min at
1000
C, which is more than adequate to anneal out the
implantation damage without greatly spreading out the
implanted doses. Typical sheet resistances were 50
for the source and drain regions, and 40 for the
polysilicon areas. Following the As
implant, a final
insulating oxide layer 2000-
˚
A thick was deposited using
low-temperature chemical-vapor deposition. Then, the con-
tact holes to the n
and polysilicon regions were defined,
and the metalization was applied and delineated. Electrical
contact directly to the shallow implanted source and drain
regions was accomplished by a suitably chosen metallurgy
to avoid junction penetration due to alloying during the
final annealing step. After metalization an annealing step
of 400
C for 20 min in forming gas was performed to
decrease the fast-state density.
Fig. 5. Predicted substrate doping profile for basic ion-implanted
device design for 40 keV B
11
ions implanted through the 350-
˚
A
gate insulator.
VI. ONE-DIMENSIONAL (LONG CHANNEL)ANALYSIS
The substrate doping profile for the 40 keV, 6.7 10
atoms/cm channel implant incident on the 350-
˚
A gate
oxide, is shown in Fig. 5. Since the oxide absorbs 3 percent
of the incident dose, the active dose in the silicon is
6.5
10 atoms/cm . The concentration at the time of
the implantation is given by the lightly dashed Gaussian
function added to the background doping level,
. For 40
keV B
ions, the projected range and standard deviation
were taken as 1300
˚
A and 500
˚
A, respectively [13].
After the heat treatments of the subsequent processing, the
boron is redistributed as shown by the heavier dashed line.
These predicted profiles were obtained using a computer
program developed by F. F. Morehead of our laboratories.
The program assumes that boron atoms diffusing in the
silicon reflect from the silicon-oxide interface and thereby
raise the surface concentration. For modeling purposes
it is convenient to use a simple, idealized, step-function
representation of the doping profile, as shown by the solid
line in Fig. 5. The step profile approximates the final
predicted profile rather well and offers the advantage that
it can be described by a few simple parameters. The three
profiles shown in Fig. 5 all have the same active dose.
Using the step profile, a model for determining threshold
voltage has been developed from piecewise solutions of
Poisson’s equation with appropriate boundary conditions
[11]. The one-dimensional model considers only the vertical
dimension and cannot account for horizontal short-channel
effects. Results of the model are shown in Fig. 6 which
plots the threshold voltage versus source-to-substrate bias
672 PROCEEDINGS OF THE IEEE, VOL. 87, NO. 4, APRIL 1999
