C
Cheng-Kok Koh
Researcher at Purdue University
Publications - 186
Citations - 4604
Cheng-Kok Koh is an academic researcher from Purdue University. The author has contributed to research in topics: Routing (electronic design automation) & Matrix (mathematics). The author has an hindex of 35, co-authored 186 publications receiving 4461 citations. Previous affiliations of Cheng-Kok Koh include Applied Science Private University & University of California, Los Angeles.
Papers
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Journal ArticleDOI
Performance optimization of VLSI interconnect layout
TL;DR: A comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance V LSI circuit design under the deep submicron fabrication technologies.
Proceedings ArticleDOI
Interconnect design for deep submicron ICs
TL;DR: A unified approach that considers topology optimization, wiresizing optimization, and waveform optimization simultaneously, and is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot, and routing cost.
Journal ArticleDOI
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
TL;DR: Compared to postfloorplan approach, the peak power-supply noise can be reduced by as much as 40% and the decap budget can be reduction by asMuch as 21% by using noise-aware floorplanning methodology.
Proceedings ArticleDOI
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Cheng-Kok Koh,Patrick H. Madden +1 more
TL;DR: A new routing paradigm that strikes at the root of the interconnect problem by reducing wire lengths directly is explored, and a non-Manhattan Steiner tree heuristic is presented, obtaining wire length reductions of much as 17% on average, when compared to rectilinear topologies.
Journal ArticleDOI
Bounded-skew clock and Steiner routing
TL;DR: This work studies the minimum-cost bounded-skew routing tree problem under the pathlength (linear) and Elmore delay models and proposes a new Greedy-BST/DME algorithm which combines the merging region computation with topology generation.