Journal ArticleDOI
Performance optimization of VLSI interconnect layout
Reads0
Chats0
TLDR
A comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance V LSI circuit design under the deep submicron fabrication technologies.About:
This article is published in Integration.The article was published on 1996-11-01. It has received 324 citations till now. The article focuses on the topics: Topology optimization & Circuit design.read more
Citations
More filters
Proceedings ArticleDOI
Interconnect-power dissipation in a microprocessor
TL;DR: The characterization of interconnect power in a state-of-the-art high-performance microprocessor designed for power efficiency shows the obtainable benefits of tuning physical design algorithms to save power.
Journal ArticleDOI
Nano/CMOS architectures using a field-programmable nanowire interconnect
TL;DR: The field-programmable nanowire interconnect (FPNI) as discussed by the authors enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices.
Book
On-Chip Communication Architectures: System on Chip Interconnect
Sudeep Pasricha,Nikil Dutt +1 more
TL;DR: This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design, and will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on- chip communication architectures.
Journal ArticleDOI
Equivalent Elmore delay for RLC trees
TL;DR: Closed-form solutions for the 50% delay, rise time, overshoots, and settling time of signals in an RLC tree are presented and have significantly improved accuracy as compared to the Elmore delay for an overdamped response.
Journal ArticleDOI
Digital Circuit Optimization via Geometric Programming
TL;DR: A method for digital circuit optimization based on formulating the problem as a geometric program or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved.
References
More filters
Journal ArticleDOI
A note on two problems in connexion with graphs
TL;DR: A tree is a graph with one and only one path between every two nodes, where at least one path exists between any two nodes and the length of each branch is given.
Journal ArticleDOI
On the shortest spanning subtree of a graph and the traveling salesman problem
TL;DR: Kurosh and Levitzki as discussed by the authors, on the radical of a general ring and three problems concerning nil rings, Bull Amer Math Soc vol 49 (1943) pp 913-919 10 -, On the structure of algebraic algebras and related rings.