C
Chittoor Parthasarathy
Researcher at STMicroelectronics
Publications - 52
Citations - 2040
Chittoor Parthasarathy is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Negative-bias temperature instability & CMOS. The author has an hindex of 16, co-authored 52 publications receiving 1946 citations. Previous affiliations of Chittoor Parthasarathy include Centre national de la recherche scientifique.
Papers
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Journal ArticleDOI
Review on high-k dielectrics reliability issues
G. Ribes,J. Mitard,M. Denais,Sylvie Bruyere,Frederic Monsieur,Chittoor Parthasarathy,Emmanuel Vincent,Gerard Ghibaudo +7 more
TL;DR: In this article, the authors review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results, showing that the reliability of Hf-based materials is influenced both by the interfacial layer as well as the high k layer.
Journal ArticleDOI
NBTI degradation: From physical mechanisms to modelling
TL;DR: An overview of the evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented and a physical model is proposed which could be used to more accurately predict the transistor degradation.
Proceedings ArticleDOI
NBTI degradation: From transistor to SRAM arrays
Vincent Huard,Chittoor Parthasarathy,C. Guerin,T. Valentin,E. Pion,M. Mammasse,Nicolas Planes,L. Camus +7 more
TL;DR: In this paper, a composite model was proposed to physically explain the mean pMOS threshold voltage shift induced by NBTI degradation at transistor level in a quantitative way, which was extended to include the statistical variations introduced by intrinsic fluctuations.
Journal ArticleDOI
A thorough investigation of MOSFETs NBTI degradation
Vincent Huard,M. Denais,F. Perrier,Nathalie Revil,Chittoor Parthasarathy,Alain Bravaix,Emmanuel Vincent +6 more
TL;DR: An overview of evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented and a physical model is proposed which could be used to more accurately predict the transistor degradation.
Journal ArticleDOI
Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide
M. Denais,Vincent Huard,Chittoor Parthasarathy,G. Ribes,F. Perrier,Nathalie Revil,Alain Bravaix +6 more
TL;DR: In this article, the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide were investigated and a possible explanation for all configurations has been suggested.