The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

https://iopscience.iop.org/article/10.1088/0034-4885/69/2/R02/pdf

High dielectric constant gate oxides for metal oxide Si transistors

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

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A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Nanotechnology is providing new solutions and opportunities to ensure sustainable energy and environments for the future. Materials of nanofiberous morphology are attractive to solve numerous energy and environmental issues. Nanofibers can be effectively produced by electrospinning, which is a simple and low cost technique. In addition, electrospinning allows the production of nanofibers from various materials e.g. organics and inorganics in different configurations and assemblies. This is highly beneficial for energy devices, where inorganic materials especially metal oxides can be synthesized and electrospun, improving conducting and ceramic properties. Excitonic solar cells fabricated with aligned nanofiberous metal oxide electrodes provide higher solar–electric energy conversion efficiency, whereas fuel cells made with nanofiberous electrodes enable uniform dispersion of catalysts, and thus increase electrocatalytic activity to obtain higher chemical–electric energy conversion efficiency. The nanofibers used in filtration membranes for environmental remediation, minimize the pressure drop and provide better efficiency than conventional fiber mats. The large surface area-to-volume ratio of nanofiber membranes allows greater surface adsorption of contaminants from air and water, and increases the life-time of the filtration media. This review highlights the potential and application of electrospun nanofiberous materials for solving critical energy and environmental issues.

Electrospun nanofibers in energy and environmental applications

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

/pdf/finfets-and-other-multi-gate-transistors-541arp307w.pdf

FinFETs and Other Multi-Gate Transistors

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

Review on high-k dielectrics reliability issues

This paper provides a close investigation of the gate oxide failure for thickness below 24/spl Aring/. At first, the failure detection is discussed showing that its manifestation is not catastrophic any more. Then, the wear-out beginning at the failure occurrence is studied. It highlights the path conduction aging whose progressiveness is found to be mainly gate voltage driven. At last, progressiveness dynamics is investigated and a methodology is developed to rigorously relax the reliability criterion following applications.

A thorough investigation of progressive breakdown in ultra-thin oxides. Physical understanding and application for industrial reliability assessment

This work gives an insight into the degradation mechanisms during a negative bias instability stress on ultrathin oxides (t/sub ox/=20 /spl Aring/). The generation of interface traps and oxide defects is shown to impact parameters such as the threshold voltage. Their generation is linked to the release of hydrogen species at the interface according to the hydrogen release model. Only hot holes can be trapped by the anode hole injection phenomenon.

Evidence for hydrogen-related defects during NBTl stress in p-MOSFETs

MIM capacitance variation under electrical stress

This paper discusses different statistical approaches for the quasi-breakdown phenomenon. In particular, a novel methodology based on the idea that breakdown and quasi-breakdown are competing mechanisms and that they have to be separately analyzed, is developed and well validated for oxide thickness ranging from 3.5 down to 2.5 nm. This methodology is demonstrated to well explain all the quasi-breakdown rate variations with temperature, voltage, area and oxide thickness. Moreover, this new approach enables to rigorously determine the quasi-breakdown acceleration factor with temperature and electric field, which have been found to be different from the breakdown ones. As a result, and confirmed by the difference observed between the obtained time to breakdown and time to quasi-breakdown spreads, the defects at the origin of both phenomena have to be different. Finally, a reliability assessment methodology is presented enabling a proper analysis of both phenomena for reliability evaluation and lifetime prediction.

Sylvie Bruyere

Papers

Review on high-k dielectrics reliability issues

A thorough investigation of progressive breakdown in ultra-thin oxides. Physical understanding and application for industrial reliability assessment

Evidence for hydrogen-related defects during NBTl stress in p-MOSFETs

MIM capacitance variation under electrical stress

Quasi-breakdown in ultra-thin SiO/sub 2/ films: occurrence characterization and reliability assessment methodology