The European Telecommunications Standards Institute (ETSI) has introduced the paradigm of Multi-Access Edge Computing (MEC) to enable efficient and fast data processing in mobile networks. Among other technological requirements, security and privacy are significant factors in the realization of MEC deployments. In this paper, we analyse the security and privacy of the MEC system. We introduce a thorough investigation of the identification and the analysis of threat vectors in the ETSI standardized MEC architecture. Furthermore, we analyse the vulnerabilities leading to the identified threat vectors and propose potential security solutions to overcome these vulnerabilities. The privacy issues of MEC are also highlighted, and clear objectives for preserving privacy are defined. Finally, we present future directives to enhance the security and privacy of MEC services.

/pdf/survey-on-multi-access-edge-computing-security-and-privacy-5epo4z3o46.pdf

Survey on Multi-Access Edge Computing Security and Privacy

The goal of physical layer security (PLS) is to make use of the properties of the physical layer—including the wireless communication medium and/or the transceiver hardware—to enable critical aspects of secure communications. In particular, PLS can be employed to provide (a) node authentication, (b) message authentication, and (c) message confidentiality. Unlike the corresponding classical cryptographic approaches which are all based on computational security, PLS’s added strength is that it is based on information theoretic security, in which no limitation with respect to the opponent’s computational power is assumed and is therefore inherently quantum resistant. In this survey, we review the aforementioned fundamental aspects of PLS, starting with node authentication, moving to the information theoretic characterization of message integrity, and finally, discussing message confidentiality both in the secret key generation from shared randomness and from the wiretap channel point of view. The aim of this review is to provide a comprehensive road-map on important relevant results by the authors and other contributors and discuss open issues on the applicability of PLS in sixth generation systems.

Physical Layer Security: Authentication, Integrity and Confidentiality

With the emergence of 5G low-latency applications, such as haptics and V2X, low-complexity and low-latency security mechanisms are needed. Promising lightweight mechanisms include physical unclonable functions (PUF) and secret key generation (SKG) at the physical layer, as considered in this paper. In this framework, we propose (i) a zero round trip time (0-RTT) resumption authentication protocol combining PUF and SKG processes, (ii) a novel authenticated encryption (AE) using SKG, and (iii) pipelining of the AE SKG and the encrypted data transfer in order to reduce latency. Implementing the pipelining at PHY, we investigate a parallel SKG approach for multi-carrier systems, where a subset of the subcarriers are used for SKG and the rest for data transmission. The optimal solution to this PHY resource allocation problem is identified under security, power, and delay constraints, by formulating the subcarrier scheduling as a subset-sum 0−1 knapsack optimization. A heuristic algorithm of linear complexity is proposed and shown to incur negligible loss with respect to the optimal dynamic programming solution. All of the proposed mechanisms have the potential to pave the way for a new breed of latency aware security protocols.

/pdf/authenticated-secret-key-generation-in-delay-constrained-1yzm2isxa5.pdf

Authenticated secret key generation in delay-constrained wireless systems

Quantum dot cellular automata (QCA) constitute an emergent nanoscale-based digital nanoelectronics technology with comprehensive applications in nanocomputing based on the small nanometer size of such circuits and their ultralow power consumption, fast operation, and high clock frequency in comparison with transistor-based complementary metal–oxide–semiconductor (CMOS) technologies. A novel design for edge-triggered synchronous J-K flip-flop (FF) and D (data or delay) flip-flop memory elements based on QCA cells with quantum wires is presented herein. The proposed design has fewer QCA cells and lower latency and area and uses the coplanar crossover method to overcome the complexity of multilayer quantum wire crossing. The design is analyzed to determine the average output polarization (AOP) of the edge-triggered synchronous D-FF and JK-FF at different temperature levels and the optimized energy dissipation. The layout design and computational simulation of the circuit are carried out using QCADesigner V. 2.0.3 software, while the energy dissipation is analyzed using the QCADesigner-E V. 2.2 tool.

An efficient design of edge-triggered synchronous memory element using quantum dot cellular automata with optimized energy dissipation

Filling up forms at post offices, railway counters, and for application of jobs has become a routine for modern people, especially in a developing country like India. Research on automation for the recognition of such handwritten forms has become mandatory. This applies more for a multilingual country like India. In the present work, we use readily available pre-trained Convolutional Neural Network (CNN) architectures on four different Indic scripts, viz. Bangla, Devanagari, Oriya, and Telugu to achieve a satisfactory recognition rate for handwritten Indic numerals. Furthermore, we have mixed Bangla and Oriya numerals and applied transfer learning for recognition. The main objective of this study is to realize how good a CNN model trained on an entire different dataset (of natural images) works for small and unrelated datasets. As a part of practical application, we have applied the proposed approach to recognize Bangla handwritten pin codes after their extraction from postal letters.

A Study on the Effect of CNN-Based Transfer Learning on Handwritten Indic and Mixed Numeral Recognition.

In the diverse, chaotic environment of the Internet of Things (IoT), the overlooked security issues in device design invite the biggest threat to adopt IoT due to its botnet. Being resource and computation intensive the traditional encryption based protocols are not suitable for low-end IoT devices. The most uncontrolled environment of IoT application makes it vulnerable to tampering and invasive attacks leading IoT-bots. In this context, Physically Unclonable Functions (PUFs) can provide the desired security at the hardware level to ensure the root of trust extracting the intrinsic physical variation of devices. Most of the IoT devices utilize WiFi technology for connectivity. However, current WiFi protocols are not sufficient to provide the desired security against the various threats, like MAC-spoofing, de-authentication, rogue access point, etc. Since IoT devices are deployed mostly in the uncontrolled environment, they are highly susceptible to those threats. Few PUF based authentication protocols are investigated towards the IoT security. However, these are not viable due to its resource and computation constraints in the context of WiFi. In this paper, a PUF based lightweight protocol is proposed which establishes the secure connection utilizing three pairs of challenge-response and generates a random number as a seed key used by the underlying WiFi protocol. Security analysis of the proposed protocol proves its effectiveness while incurs less resource and computation overhead.

A PUF based Light Weight Protocol for Secure WiFi Authentication of IoT devices

Fast pace growth in the IC industry is facing the challenges of feature size reduction which in turn demands an alternative to current CMOS VLSI. Quantum-dot cellular automata are emerging as one o...

An efficient clocking scheme for quantum-dot cellular automata

Field Programmable Gate Array (FPGA) has become an attractive platform for faster growth of the Internet of Things (IoT). However, like other technologies, FPGA needs resilience against various threats. In addition, the un-monitored environment makes IoT devices more vulnerable. In this context, Physically Unclonable Function (PUF) can provide a low-cost and unique security solution over the costly conventional cryptographic system. Although Arbiter PUF (APUF) is the most suitable PUF variant for IoT, implementing a high-quality APUF on FPGA has been proved to be challenging. To date, programmable delay logic (PDL) is the widely adopted primitive to design APUF on FPGA. However, the implementation of PDL based APUF demands hard-macro feature of CAD tool which limits flexibility of the design. Also, such designs require fine-tuning to achieve PUF characteristics. This paper introduces a new switching structure named path changing switch (PCS) which is easily implementable on FPGA, and this PCS is used here to design APUF instead of the PDL. Further, the directed routing constraint is used to implement an exemplary APUF which possess better flexibility. Also, a new structure of the enable logic and manual routing is used to reduce the delay-bias. Finally, the design has been implemented over 15 different Spartan 3E FPGA boards. Experimental results show that the proposed design outperforms the PDL based APUFs in terms of PUF quality metrics without using additional fine-tuning. Also, the implemented design shows significant tolerance against temperature variations.

An Efficient Implementation of Arbiter PUF on FPGA for IoT Application

Hardware Trojans are intentional addition of malicious logic into a normal circuit which is widely regarded as one of the biggest concerns for IC industry due to the presence of a global supply chain. Being very small in size, Trojans remain dormant during manufacturing tests and only gets activated during operational mode for a rare input signal combination. Existing stuck-at-fault testing methods are insufficient for Trojan detection. In this context, a methodology to produce test vector is proposed in this work which generates rare signals inside a circuit. The proposed work uses transition probability to find rare activity nets. A set of test vectors are generated based on the impact of primary inputs on rare nets to stimulate rare signals across the netlist. The effects of final test vectors are verified with ISCAS-85 benchmark circuits and also compared with the performance of random vectors. Simulation result advocates the significance of the proposed test vectors in terms of rare net excitation.

A Novel Test Vector Generation Method for Hardware Trojan Detection

Hardware Trojan has become a serious security issue in recent times for both integrated chip (IC) industry and government due to the separation of the design phase and manufacturing phase of the IC industrial model. Hardware Trojan is a malicious logic added to a functional system by an adversary with an intention of system malfunction or failure. Due to its stealthy nature, traditional testing algorithms are not sufficient to detect such Trojans. Few attempts have been made for the detection of hardware trojan augmenting extra logic module in design phase inside the main circuit. However, those approaches suffer from various issues such as huge insertion overhead, high time complexity etc. In this context, an efficient methodology by inserting XOR gates inside a netlist is proposed here to detect the presence of Trojan. Experimental result shows that our proposed method achieved significant improvement in terms of number of transitions at possible vulnerable nets while overcoming the limitations of the previous works. Transition probability of the vulnerable nets has increased up to 5 times which is validated by various ISCAS-89 benchmark circuits.

https://ieeexplore.ieee.org/iel7/8698774/8703880/08704062.pdf

Mahabub Hasan Mahalat

Papers

A PUF based Light Weight Protocol for Secure WiFi Authentication of IoT devices

An efficient clocking scheme for quantum-dot cellular automata

An Efficient Implementation of Arbiter PUF on FPGA for IoT Application

A Novel Test Vector Generation Method for Hardware Trojan Detection

XOR based Methodology to Detect Hardware Trojan utilizing the Transition Probability