M
Mrinal Goswami
Researcher at National Institute of Technology, Durgapur
Publications - 35
Citations - 383
Mrinal Goswami is an academic researcher from National Institute of Technology, Durgapur. The author has contributed to research in topics: Quantum dot cellular automaton & Logic gate. The author has an hindex of 8, co-authored 25 publications receiving 266 citations. Previous affiliations of Mrinal Goswami include University of Petroleum and Energy Studies.
Papers
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Journal ArticleDOI
Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability
TL;DR: The experimentation establishes that the proposed RALU outperforms the conventional reversible ALU in terms of programming flexibility and testability and is able to achieve 100% fault tolerance in the presence of single missing or additional cell defects in QCA layout.
Journal ArticleDOI
Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers
TL;DR: The Quantum dot Cellular Automata (QCA) can be such an architecture at nano-scale and thus emerges as a viable alternative for the current CMOS VLSI and its effectiveness is further established through synthesis of configurable logic block (CLB) for field programmable gate arrays (FPGAs).
Journal ArticleDOI
Design of Testable Adder in Quantum‐dot Cellular Automata with Fault Secure Logic
TL;DR: A novel parity preserving testable adder in QCA which tackles the internal fault within the gate efficiently resulting a testable circuit, and signifies the dominance of t-Adder in low power consumption.
Proceedings ArticleDOI
Efficient realization of digital logic circuit using QCA multiplexer
TL;DR: In this paper, the design capability of the multiplexer in QCA is investigated implementing XOR, XNOR logic gate and arithmetic logic unit, and the design of efficient sequential circuits like D latch, T latch, D flip-flop, Scan flipflop and shift registers are designed.
Journal ArticleDOI
An efficient clocking scheme for quantum-dot cellular automata
TL;DR: A robust, efficient and scalable (RES) clocking scheme for QCA circuit is proposed which can facilitate three directional information flow within a single clock zone and overcome the complex multilayer wire crossing with most promising coplanar crossover.