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Open AccessJournal ArticleDOI

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

TLDR
Eyeriss as mentioned in this paper is an accelerator for state-of-the-art deep convolutional neural networks (CNNs) that optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, by reconfiguring the architecture.
Abstract
Eyeriss is an accelerator for state-of-the-art deep convolutional neural networks (CNNs). It optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, for various CNN shapes by reconfiguring the architecture. CNNs are widely used in modern AI systems but also bring challenges on throughput and energy efficiency to the underlying hardware. This is because its computation requires a large amount of data, creating significant data movement from on-chip and off-chip that is more energy-consuming than computation. Minimizing data movement energy cost for any CNN shape, therefore, is the key to high throughput and energy efficiency. Eyeriss achieves these goals by using a proposed processing dataflow, called row stationary (RS), on a spatial architecture with 168 processing elements. RS dataflow reconfigures the computation mapping of a given shape, which optimizes energy efficiency by maximally reusing data locally to reduce expensive data movement, such as DRAM accesses. Compression and data gating are also applied to further improve energy efficiency. Eyeriss processes the convolutional layers at 35 frames/s and 0.0029 DRAM access/multiply and accumulation (MAC) for AlexNet at 278 mW (batch size $N = 4$ ), and 0.7 frames/s and 0.0035 DRAM access/MAC for VGG-16 at 236 mW ( $N = 3$ ).

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Citations
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TL;DR: In this article, the authors presented an implementation of a deep learning inference in Field Programmable Gate Array (FPGA) to predict diabetic Mellitus (DM) and achieved an accuracy of 91.15%.
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Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models.

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An Edge 3D CNN Accelerator for Low-Power Activity Recognition

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Efficient Hardware Architectures for 1D- and MD-LSTM Networks

TL;DR: This article presents for the first time a hardware architecture for MD-LSTM, and shows a trade-off analysis for accuracy and hardware cost for various precisions, and presents a new DRAM-PIM architecture for 1D-L STM targeting energy efficient compute platforms such as portable devices.
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DRACO: Co-Optimizing Hardware Utilization, and Performance of DNNs on Systolic Accelerator

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