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Open AccessJournal ArticleDOI

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

TLDR
Eyeriss as mentioned in this paper is an accelerator for state-of-the-art deep convolutional neural networks (CNNs) that optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, by reconfiguring the architecture.
Abstract
Eyeriss is an accelerator for state-of-the-art deep convolutional neural networks (CNNs). It optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, for various CNN shapes by reconfiguring the architecture. CNNs are widely used in modern AI systems but also bring challenges on throughput and energy efficiency to the underlying hardware. This is because its computation requires a large amount of data, creating significant data movement from on-chip and off-chip that is more energy-consuming than computation. Minimizing data movement energy cost for any CNN shape, therefore, is the key to high throughput and energy efficiency. Eyeriss achieves these goals by using a proposed processing dataflow, called row stationary (RS), on a spatial architecture with 168 processing elements. RS dataflow reconfigures the computation mapping of a given shape, which optimizes energy efficiency by maximally reusing data locally to reduce expensive data movement, such as DRAM accesses. Compression and data gating are also applied to further improve energy efficiency. Eyeriss processes the convolutional layers at 35 frames/s and 0.0029 DRAM access/multiply and accumulation (MAC) for AlexNet at 278 mW (batch size $N = 4$ ), and 0.7 frames/s and 0.0035 DRAM access/MAC for VGG-16 at 236 mW ( $N = 3$ ).

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Citations
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Proceedings ArticleDOI

Hardware-Software Co-design Approach for Deep Learning Inference

TL;DR: This paper proposes a heterogeneous hardware-software based architecture for performing inference in feed-forward neural networks which is capable of early exiting through intermediate exits according to the difficulty level of the input.
Proceedings ArticleDOI

High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator

TL;DR: A high utilization energy-aware real-time inference deep convolutional neural network accelerator, which outperforms the current accelerators and reduces a generous amount of data transfer on the specific module, ECNN.
Patent

3D array arranged for memory and in-memory sum-of-products operations

Lue Hang-Ting
TL;DR: In this article, a 3D array of cells arranged for execution of a sum-of-products operation, the cells in the array disposed in cross-points of a plurality of vertical lines and a pluralityof horizontal lines, having programmable conductances.
Proceedings ArticleDOI

iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS

TL;DR: The paper presents iFPNA, instruction-and-fabric programmable neuron array: a general-purpose deep learning accelerator that achieves both energy efficiency and flexibility.
Proceedings ArticleDOI

CASH: compiler assisted hardware design for improving DRAM energy efficiency in CNN inference

TL;DR: This paper presents CASH, a compiler-assisted hardware solution that eliminates redundant data-movement to and from the main memory and, therefore, reduces main memory bandwidth and energy consumption.
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