Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
TLDR
Eyeriss as mentioned in this paper is an accelerator for state-of-the-art deep convolutional neural networks (CNNs) that optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, by reconfiguring the architecture.Abstract:
Eyeriss is an accelerator for state-of-the-art deep convolutional neural networks (CNNs). It optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, for various CNN shapes by reconfiguring the architecture. CNNs are widely used in modern AI systems but also bring challenges on throughput and energy efficiency to the underlying hardware. This is because its computation requires a large amount of data, creating significant data movement from on-chip and off-chip that is more energy-consuming than computation. Minimizing data movement energy cost for any CNN shape, therefore, is the key to high throughput and energy efficiency. Eyeriss achieves these goals by using a proposed processing dataflow, called row stationary (RS), on a spatial architecture with 168 processing elements. RS dataflow reconfigures the computation mapping of a given shape, which optimizes energy efficiency by maximally reusing data locally to reduce expensive data movement, such as DRAM accesses. Compression and data gating are also applied to further improve energy efficiency. Eyeriss processes the convolutional layers at 35 frames/s and 0.0029 DRAM access/multiply and accumulation (MAC) for AlexNet at 278 mW (batch size $N = 4$ ), and 0.7 frames/s and 0.0035 DRAM access/MAC for VGG-16 at 236 mW ( $N = 3$ ).read more
Citations
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Dynamic Dataflow Scheduling and Computation Mapping Techniques for Efficient Depthwise Separable Convolution Acceleration
TL;DR: In this paper, the authors proposed two efficient dynamic design techniques, i.e., adaptive row-based dataflow scheduling and adaptive computation mapping, to achieve a much better trade-off between hardware efficiency and performance for DSC-based lightweight CNN accelerator.
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DIAN: differentiable accelerator-network co-search towards maximal DNN efficiency
Yongan Zhang,Yonggan Fu,Weiwen Jiang,Chaojian Li,Haoran You,Meng Li,Vikas Chandra,Yingyan Lin +7 more
TL;DR: DIAN as discussed by the authors is a differentiable accelerator-network co-search framework for automatically searching for matched networks and accelerators to maximize both the accuracy and efficiency, which is applicable to both FPGA-and ASIC-based DNN accelerators.
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An Efficient FIFO Based Accelerator for Convolutional Neural Networks
TL;DR: An improved architecture to process the convolution layers in a CNN that takes advantage of sparsity in CNN layer’s inputs and outputs to achieve performance improvement and is able to exceed the performance of state-of-the-art architectures.
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