Journal ArticleDOI
RF and analogue performance investigation of DG tunnel FET
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TLDR
In this paper, the performance of a double-gate tunnel FET (DGTFET) was investigated with the help of a device simulator, and the variation of different analogue and RF device performance parameters were investigated, such as transconductance-to-drain-current ratio (gm/Id), intrinsic gain, cut-off frequency (fT), and maximum frequency of oscillation (fmax) as a function of channel length.Abstract:
In this letter, the analogue and RF performance of a silicon double-gate tunnel FET (DGTFET) is reported. With the help of a device simulator, the variation of different analogue and RF device performance parameters are investigated, such as transconductance-to-drain-current ratio (gm/Id), intrinsic gain (gm/gds), cut-off frequency (fT), and maximum frequency of oscillation (fmax) as a function of channel length, are studied. Our results show that the reduction of channel length results in an improvement in the RF performance parameters of the device and deterioration of the analogue performance parameters of the device, clearly indicating a necessary design trade-off between the RF (bandwidth) and analogue performances (power efficiency). The investigation presented here exhibits a valuable result that the DGTFET devices with optimised gate length are suitable for low-power analogue and RF applications.read more
Citations
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Journal ArticleDOI
Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET
TL;DR: In this article, the effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire (NW) Tunnel FET (TFET) was analyzed.
Journal ArticleDOI
Performance analysis of heterojunction tunnel FET device with variable Temperature
Abstract: In this paper, the analysis of SiGe source-based heterojunction Tunnel FET device is reported. The parameters like transconductance (gm), device efficiency (gm/ID), gate-source capacitance (CGS), gate-drain capacitance (CGD), cut-off frequency (fT), and gain-bandwidth product (GBP) are studied. DC, as well as AC simulations, have been performed on the proposed device. We have achieved an ON current of 0.537 mA/µm and an OFF current of 13 fA/µm, thus achieving ION/IOFF ratio as 3.72 × 1010. The values obtained for the transconductance are 0.68 milliSiemens, cut-off frequency is 446 GHz, gate-source capacitance is 0.387 femto Farads, and gate drain capacitance is 0.694 femtoFarads. The lower values of parasitic capacitances enable the device to be helpful for the low power and analog/RF applications even at high frequencies. The device has also been investigated for the temperature analysis concerning the drain current and the capacitance calculations. It was observed that the OFF currents are strongly dependent on the temperature in the drain current characteristics of the device. All the simulations have been performed on Visual TCAD (licensed version 1.9.2–3).
Journal ArticleDOI
Controlling the ambipolarity and improvement of RF performance using Gaussian Drain Doped TFET
TL;DR: In this article, Gaussian doping is used in the drain region of conventional gate-drain overlap TFETs to control the tunneling of electrons from the valence band of channel to the conduction band of drain.
Journal ArticleDOI
A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps
Journal ArticleDOI
Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate
TL;DR: In this paper, a dual metallic material gate heterostructure junctionless tunnel field effect transistor (DMMG-HJLTFET) was proposed and investigated to improve the band to band tunneling (BTBT) rate, and a sandwich stack (GaAs/Si/GaAs) at the drain region to suppress the OFF-state current and ambiplolar current.
References
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Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
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Effect of gate engineering in double-gate MOSFETs for analog/RF applications
TL;DR: It is demonstrated that TM-DG MOSFET can be a viable option to enhance the performance of SOI technology for high-frequency analog applications.
Journal ArticleDOI
Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications
TL;DR: In this article, the analog performance of a double-gate n-type tunnel field effect transistor (n-TFET) with a relatively small body thickness (10 nm) was investigated.
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Dual- $k$ Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs
TL;DR: In this paper, a dual-k spacer is proposed for underlap and nonunderlap n-channel FETs for the first time using extensive device simulations and it is shown that the dual k spacer improves the performance of underlap structures.
Journal ArticleDOI
Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model
TL;DR: In this article, the authors report a systematic, quantitative investigation of analog and RF performance of cylindrical surrounding-gate (SRG) silicon MOSFETs and derive a pseudo-two-dimensional (2D) approach applying Gauss's law in the channel region.