C
C. Kuo
Researcher at University of California, Berkeley
Publications - 9
Citations - 2840
C. Kuo is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Short-channel effect & Gate oxide. The author has an hindex of 7, co-authored 9 publications receiving 2685 citations.
Papers
More filters
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Proceedings ArticleDOI
Sub 50-nm FinFET: PMOS
Xuejue Huang,Wen-Chin Lee,C. Kuo,D. Hisamoto,Leland Chang,J. Kedzierski,E. Anderson,Hideki Takeuchi,Yang-Kyu Choi,K. Asano,Vivek Subramanian,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +13 more
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect, and a 45 nm gate-length PMOS FinEET is presented.
Journal ArticleDOI
Sub-50 nm P-channel FinFET
Xuejue Huang,Wen-Chin Lee,C. Kuo,Digh Hisamoto,Leland Chang,J. Kedzierski,Erik H. Anderson,Hideki Takeuchi,Yang-Kyu Choi,K. Asano,Vivek Subramanian,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +13 more
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects, which shows good performance down to a gate-length of 18 nm.
Proceedings ArticleDOI
A capacitorless double-gate DRAM cell design for high density applications
C. Kuo,Tsu-Jae King,Chenming Hu +2 more
TL;DR: In this article, a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design is investigated and the soft error problems are discussed. But careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.