D
Digh Hisamoto
Researcher at Hitachi
Publications - 113
Citations - 4669
Digh Hisamoto is an academic researcher from Hitachi. The author has contributed to research in topics: MOSFET & Field-effect transistor. The author has an hindex of 25, co-authored 108 publications receiving 4428 citations. Previous affiliations of Digh Hisamoto include Renesas Electronics & Tokyo Institute of Technology.
Papers
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Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
Sub-50 nm P-channel FinFET
Xuejue Huang,Wen-Chin Lee,C. Kuo,Digh Hisamoto,Leland Chang,J. Kedzierski,Erik H. Anderson,Hideki Takeuchi,Yang-Kyu Choi,K. Asano,Vivek Subramanian,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +13 more
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects, which shows good performance down to a gate-length of 18 nm.
Proceedings ArticleDOI
A folded-channel MOSFET for deep-sub-tenth micron era
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,E. Anderson,Hideki Takeuchi,K. Asano,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +8 more
TL;DR: In this paper, a quasi-planar fold-channel transistor structure was proposed for the vertical double-gate SOI MOSFETs, which improved the short channel effect immunities.
Proceedings ArticleDOI
A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET
TL;DR: A fully depleted lean channel transistor (DELTA) with a gate structure and vertical ultrathin SOI (silicon-on-insulator) structure with selective field oxide is reported in this paper.
Journal ArticleDOI
An experimental 1.5-V 64-Mb DRAM
Y. Nakagome,Tanaka Haruhiko,Kan Takeuchi,E. Kume,Y. Watanabe,Toru Kaga,Yoshifumi Kawamoto,Fumio Murai,R. Izawa,Digh Hisamoto,T. Kisu,Takashi Nishida,Eiji Takeda,K. Itoh +13 more
TL;DR: In this paper, an accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed to reduce data transmission delay.