Marina Tosi

TL;DR: In this paper, a novel cell structure for chalcogenide-based nonvolatile phase-change memories is presented, which is fully compatible with an advanced CMOS technology, is highly manufacturable and allows to optimize array density and cell performance.

TL;DR: A detailed investigation of the reliability aspects in nonvolatile phase-change memories (PCM) is presented, covering the basic aspects related to high density array NVM, i.e., data retention, endurance, program and read disturbs.

TL;DR: Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone phase-change memory with standard CMOS fabrication process.

TL;DR: An 8Mb Non-Volatile Memory Demonstrator incorporating a novel 0.32 /spl mu/m/sup 2/ Phase-Change Memory (PCM) cell using a Bipolar Junction Transistor (BJT) as selector and integrated into a 3V 0.18 /splmu/m CMOS technology is presented in this article.

TL;DR: In this paper, a /spl mu/trench Phase-Change Memory (PCM) cell with MOSFET selector and its integration in a 4-Mb experimental chip fabricated in 0.18/spl µ/m CMOS technology are presented.