Journal ArticleDOI
Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm
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TLDR
This work curve fit second and third-order polynomials to circuit delay, energy, and power dissipation results based on HSpice simulations utilizing the Predictive Technology Model (PTM) and International Technology Roadmap for Semiconductors (ITRS) models.About:
This article is published in Integration.The article was published on 2017-06-01. It has received 211 citations till now. The article focuses on the topics: International Technology Roadmap for Semiconductors & Scaling.read more
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Journal ArticleDOI
Electronic-photonic arithmetic logic unit for high-speed computing
Zhoufeng Ying,Chenghao Feng,Zheng Zhao,Shounak Dhar,Hamed Dalir,Jiaqi Gu,Yue Cheng,Richard A. Soref,David Z. Pan,Ray T. Chen +9 more
TL;DR: An electronic-photonic computing architecture for a wavelength division multiplexing-based electronic-Photonic arithmetic logic unit, which disentangles the exponential relationship between power and clock rate, leading to an enhancement in computation speed and power efficiency as compared to the state-of-the-art transistors-based circuits.
Journal ArticleDOI
MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices
TL;DR: In this paper, the first successful demonstration of an adiabatic microprocessor based on unshunted Josephson junction (JJ) devices manufactured using a Nb/AlOx/Nb superconductor IC fabrication process was conducted.
Journal ArticleDOI
Recurrent Neural Networks: An Embedded Computing Perspective
TL;DR: Some guidelines for RNN hardware designers to support flexibility in a better manner are provided and applying algorithmic optimizations to RNN models and decreasing the memory access overhead is vital to obtain high efficiency.
Journal ArticleDOI
Res-DNN: A Residue Number System-Based DNN Accelerator Unit
TL;DR: This article proposes a technique, based on using Residue Number System (RNS), to improve the energy efficiency of Deep Neural Networks (DNNs) and suggests a Huffman-based coding for accessing the weights stored in the main memory.
Proceedings ArticleDOI
The Accelerator Wall: Limits of Chip Specialization
Adi Fuchs,David Wentzlaff +1 more
TL;DR: This work characterizes how current accelerators depend on CMOS scaling, based on a physical modeling tool that is constructed using datasheets of thousands of chips, and builds a model which projects forward to see what future gains can and cannot be enabled from chip specialization.
References
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Journal ArticleDOI
Cramming More Components Onto Integrated Circuits
TL;DR: Integrated circuits will lead to such wonders as home computers or at least terminals connected to a central computer, automatic controls for automobiles, and personal portable communications equipment as mentioned in this paper. But the biggest potential lies in the production of large systems.
Journal Article
Cramming More Components onto Integrated Circuits
TL;DR: Integrated circuits will lead to such wonders as home computers or at least terminals connected to a central computer, automatic controls for automobiles, and personal portable communications equipment as discussed by the authors. But the biggest potential lies in the production of large systems.
Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Digital integrated circuits: a design perspective
TL;DR: In this paper, the authors present a survey of the state-of-the-art in the field of digital integrated circuits, focusing on the following: 1. A Historical Perspective. 2. A CIRCUIT PERSPECTIVE.
Book
CMOS VLSI Design : A Circuits and Systems Perspective
Neil Weste,David Money Harris +1 more
TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.