Example of IEEE Journal of Solid-State Circuits format
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Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format
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Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format Example of IEEE Journal of Solid-State Circuits format
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IEEE Journal of Solid-State Circuits — Template for authors

Publisher: IEEE
Categories Rank Trend in last 3 yrs
Electrical and Electronic Engineering #54 of 693 down down by 7 ranks
journal-quality-icon Journal quality:
High
calendar-icon Last 4 years overview: 1140 Published Papers | 11983 Citations
indexed-in-icon Indexed in: Scopus
last-updated-icon Last updated: 05/07/2020
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Related Journals

open access Open Access

IEEE

Quality:  
High
CiteRatio: 6.4
SJR: 0.786
SNIP: 2.027
open access Open Access

IEEE

Quality:  
High
CiteRatio: 3.7
SJR: 0.396
SNIP: 1.133
open access Open Access
recommended Recommended

IEEE

Quality:  
High
CiteRatio: 9.7
SJR: 1.652
SNIP: 1.947

Journal Performance & Insights

Impact Factor

CiteRatio

Determines the importance of a journal by taking a measure of frequency with which the average article in a journal has been cited in a particular year.

A measure of average citations received per peer-reviewed paper published in the journal.

4.929

5% from 2018

Impact factor for IEEE Journal of Solid-State Circuits from 2016 - 2019
Year Value
2019 4.929
2018 5.173
2017 4.075
2016 4.181
graph view Graph view
table view Table view

10.5

14% from 2019

CiteRatio for IEEE Journal of Solid-State Circuits from 2016 - 2020
Year Value
2020 10.5
2019 9.2
2018 8.3
2017 7.9
2016 8.4
graph view Graph view
table view Table view

insights Insights

  • Impact factor of this journal has decreased by 5% in last year.
  • This journal’s impact factor is in the top 10 percentile category.

insights Insights

  • CiteRatio of this journal has increased by 14% in last years.
  • This journal’s CiteRatio is in the top 10 percentile category.

SCImago Journal Rank (SJR)

Source Normalized Impact per Paper (SNIP)

Measures weighted citations received by the journal. Citation weighting depends on the categories and prestige of the citing journal.

Measures actual citations received relative to citations expected for the journal's category.

2.571

12% from 2019

SJR for IEEE Journal of Solid-State Circuits from 2016 - 2020
Year Value
2020 2.571
2019 2.913
2018 2.004
2017 1.665
2016 1.604
graph view Graph view
table view Table view

2.9

1% from 2019

SNIP for IEEE Journal of Solid-State Circuits from 2016 - 2020
Year Value
2020 2.9
2019 2.875
2018 2.971
2017 2.949
2016 2.949
graph view Graph view
table view Table view

insights Insights

  • SJR of this journal has decreased by 12% in last years.
  • This journal’s SJR is in the top 10 percentile category.

insights Insights

  • SNIP of this journal has increased by 1% in last years.
  • This journal’s SNIP is in the top 10 percentile category.
IEEE Journal of Solid-State Circuits

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IEEE

IEEE Journal of Solid-State Circuits

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design,...... Read More

Engineering

i
Last updated on
04 Jul 2020
i
ISSN
0018-9200
i
Impact Factor
Very High - 4.055
i
Open Access
No
i
Sherpa RoMEO Archiving Policy
Green faq
i
Plagiarism Check
Available via Turnitin
i
Endnote Style
Download Available
i
Bibliography Name
IEEEtran
i
Citation Type
Numbered
[25]
i
Bibliography Example
C. W. J. Beenakker, “Specular andreev reflection in graphene,” Phys. Rev. Lett., vol. 97, no. 6, p.

Top papers written in this journal

Journal Article DOI: 10.1109/JSSC.1989.572629
Matching properties of MOS transistors
M.J.M. Pelgrom1, A.C.J. Duinmaijer1, A.P.G. Welbers1

Abstract:

The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching... The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. > read more read less

Topics:

Matching (statistics) (55%)55% related to the paper, Random dopant fluctuation (52%)52% related to the paper, Electronic circuit (51%)51% related to the paper
3,121 Citations
open accessOpen access Journal Article DOI: 10.1109/JSSC.1974.1050511
Design of ion-implanted MOSFET's with very small physical dimensions

Abstract:

This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is... This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected. read more read less

Topics:

Field-effect transistor (55%)55% related to the paper, MOSFET (55%)55% related to the paper, Threshold voltage (53%)53% related to the paper, Voltage source (53%)53% related to the paper, Ion implantation (52%)52% related to the paper
View PDF
3,008 Citations
open accessOpen access Journal Article DOI: 10.1109/4.126534
Low-power CMOS digital design
Anantha P. Chandrakasan1, Samuel Sheng1, Robert W. Brodersen1

Abstract:

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply volta... Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. > read more read less

Topics:

CMOS (57%)57% related to the paper, Energy consumption (56%)56% related to the paper, Logic gate (55%)55% related to the paper, Digital electronics (54%)54% related to the paper, Circuit design (52%)52% related to the paper
View PDF
2,690 Citations
open accessOpen access Journal Article DOI: 10.1109/4.658619
A general theory of phase noise in electrical oscillators
Ali Hajimiri1, Thomas H. Lee1

Abstract:

A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing... A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed. read more read less

Topics:

Phase noise (69%)69% related to the paper, Oscillator phase noise (69%)69% related to the paper, Noise (69%)69% related to the paper, Noise measurement (68%)68% related to the paper, Quantum noise (67%)67% related to the paper
View PDF
2,270 Citations
open accessOpen access Journal Article DOI: 10.1109/JSSC.2016.2616357
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
Yu-Hsin Chen1, Tushar Krishna1, Joel Emer1, Vivienne Sze1

Abstract:

Eyeriss is an accelerator for state-of-the-art deep convolutional neural networks (CNNs). It optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, for various CNN shapes by reconfiguring the architecture. CNNs are widely used in modern AI systems but also bring challenges ... Eyeriss is an accelerator for state-of-the-art deep convolutional neural networks (CNNs). It optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, for various CNN shapes by reconfiguring the architecture. CNNs are widely used in modern AI systems but also bring challenges on throughput and energy efficiency to the underlying hardware. This is because its computation requires a large amount of data, creating significant data movement from on-chip and off-chip that is more energy-consuming than computation. Minimizing data movement energy cost for any CNN shape, therefore, is the key to high throughput and energy efficiency. Eyeriss achieves these goals by using a proposed processing dataflow, called row stationary (RS), on a spatial architecture with 168 processing elements. RS dataflow reconfigures the computation mapping of a given shape, which optimizes energy efficiency by maximally reusing data locally to reduce expensive data movement, such as DRAM accesses. Compression and data gating are also applied to further improve energy efficiency. Eyeriss processes the convolutional layers at 35 frames/s and 0.0029 DRAM access/multiply and accumulation (MAC) for AlexNet at 278 mW (batch size $N = 4$ ), and 0.7 frames/s and 0.0035 DRAM access/MAC for VGG-16 at 236 mW ( $N = 3$ ). read more read less

Topics:

Dram (54%)54% related to the paper, Efficient energy use (54%)54% related to the paper, Dataflow (53%)53% related to the paper, Throughput (business) (53%)53% related to the paper, Convolutional neural network (51%)51% related to the paper
2,165 Citations
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IEEE Journal of Solid-State Circuits format uses IEEEtran citation style.

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Frequently asked questions

1. Can I write IEEE Journal of Solid-State Circuits in LaTeX?

Absolutely not! Our tool has been designed to help you focus on writing. You can write your entire paper as per the IEEE Journal of Solid-State Circuits guidelines and auto format it.

2. Do you follow the IEEE Journal of Solid-State Circuits guidelines?

Yes, the template is compliant with the IEEE Journal of Solid-State Circuits guidelines. Our experts at SciSpace ensure that. If there are any changes to the journal's guidelines, we'll change our algorithm accordingly.

3. Can I cite my article in multiple styles in IEEE Journal of Solid-State Circuits?

Of course! We support all the top citation styles, such as APA style, MLA style, Vancouver style, Harvard style, and Chicago style. For example, when you write your paper and hit autoformat, our system will automatically update your article as per the IEEE Journal of Solid-State Circuits citation style.

4. Can I use the IEEE Journal of Solid-State Circuits templates for free?

Sign up for our free trial, and you'll be able to use all our features for seven days. You'll see how helpful they are and how inexpensive they are compared to other options, Especially for IEEE Journal of Solid-State Circuits.

5. Can I use a manuscript in IEEE Journal of Solid-State Circuits that I have written in MS Word?

Yes. You can choose the right template, copy-paste the contents from the word document, and click on auto-format. Once you're done, you'll have a publish-ready paper IEEE Journal of Solid-State Circuits that you can download at the end.

6. How long does it usually take you to format my papers in IEEE Journal of Solid-State Circuits?

It only takes a matter of seconds to edit your manuscript. Besides that, our intuitive editor saves you from writing and formatting it in IEEE Journal of Solid-State Circuits.

7. Where can I find the template for the IEEE Journal of Solid-State Circuits?

It is possible to find the Word template for any journal on Google. However, why use a template when you can write your entire manuscript on SciSpace , auto format it as per IEEE Journal of Solid-State Circuits's guidelines and download the same in Word, PDF and LaTeX formats? Give us a try!.

8. Can I reformat my paper to fit the IEEE Journal of Solid-State Circuits's guidelines?

Of course! You can do this using our intuitive editor. It's very easy. If you need help, our support team is always ready to assist you.

9. IEEE Journal of Solid-State Circuits an online tool or is there a desktop version?

SciSpace's IEEE Journal of Solid-State Circuits is currently available as an online tool. We're developing a desktop version, too. You can request (or upvote) any features that you think would be helpful for you and other researchers in the "feature request" section of your account once you've signed up with us.

10. I cannot find my template in your gallery. Can you create it for me like IEEE Journal of Solid-State Circuits?

Sure. You can request any template and we'll have it setup within a few days. You can find the request box in Journal Gallery on the right side bar under the heading, "Couldn't find the format you were looking for like IEEE Journal of Solid-State Circuits?”

11. What is the output that I would get after using IEEE Journal of Solid-State Circuits?

After writing your paper autoformatting in IEEE Journal of Solid-State Circuits, you can download it in multiple formats, viz., PDF, Docx, and LaTeX.

12. Is IEEE Journal of Solid-State Circuits's impact factor high enough that I should try publishing my article there?

To be honest, the answer is no. The impact factor is one of the many elements that determine the quality of a journal. Few of these factors include review board, rejection rates, frequency of inclusion in indexes, and Eigenfactor. You need to assess all these factors before you make your final call.

13. What is Sherpa RoMEO Archiving Policy for IEEE Journal of Solid-State Circuits?

SHERPA/RoMEO Database

We extracted this data from Sherpa Romeo to help researchers understand the access level of this journal in accordance with the Sherpa Romeo Archiving Policy for IEEE Journal of Solid-State Circuits. The table below indicates the level of access a journal has as per Sherpa Romeo's archiving policy.

RoMEO Colour Archiving policy
Green Can archive pre-print and post-print or publisher's version/PDF
Blue Can archive post-print (ie final draft post-refereeing) or publisher's version/PDF
Yellow Can archive pre-print (ie pre-refereeing)
White Archiving not formally supported
FYI:
  1. Pre-prints as being the version of the paper before peer review and
  2. Post-prints as being the version of the paper after peer-review, with revisions having been made.

14. What are the most common citation types In IEEE Journal of Solid-State Circuits?

The 5 most common citation types in order of usage for IEEE Journal of Solid-State Circuits are:.

S. No. Citation Style Type
1. Author Year
2. Numbered
3. Numbered (Superscripted)
4. Author Year (Cited Pages)
5. Footnote

15. How do I submit my article to the IEEE Journal of Solid-State Circuits?

It is possible to find the Word template for any journal on Google. However, why use a template when you can write your entire manuscript on SciSpace , auto format it as per IEEE Journal of Solid-State Circuits's guidelines and download the same in Word, PDF and LaTeX formats? Give us a try!.

16. Can I download IEEE Journal of Solid-State Circuits in Endnote format?

Yes, SciSpace provides this functionality. After signing up, you would need to import your existing references from Word or Bib file to SciSpace. Then SciSpace would allow you to download your references in IEEE Journal of Solid-State Circuits Endnote style according to Elsevier guidelines.

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