N. Demaria

TL;DR: The Compact Muon Solenoid (CMS) detector at the Large Hadron Collider (LHC) at CERN as mentioned in this paper was designed to study proton-proton (and lead-lead) collisions at a centre-of-mass energy of 14 TeV (5.5 TeV nucleon-nucleon) and at luminosities up to 10(34)cm(-2)s(-1)

TL;DR: Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits, which will help address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds.

TL;DR: This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC, which integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends.

TL;DR: In this article, the authors describe the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications, which was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration.